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Tsirkin" To: Lev Kujawski Cc: qemu-devel@nongnu.org, Eduardo Habkost , John Snow , qemu-block@nongnu.org, Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , Marcel Apfelbaum , Laurent Vivier , Yanan Wang , Paolo Bonzini , Thomas Huth Subject: Re: [PATCH v3 2/2] hw/ide/piix: Ignore writes of hardwired PCI command register bits Message-ID: <20221024095844-mutt-send-email-mst@kernel.org> References: <20221007095229-mutt-send-email-mst@kernel.org> <20221024094621.512806-1-lkujaw@mailbox.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20221024094621.512806-1-lkujaw@mailbox.org> Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.503, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, Oct 24, 2022 at 09:46:19AM +0000, Lev Kujawski wrote: > > I guess this cna work but what I had in mind is much > > simpler. Add an internal property (name starting with "x-") > > enabling the buggy behaviour and set it in hw compat array. > > If set - do not touch the wmask register. > > > > post load hooks are harder to reason about. > > Thanks again for the review and clarification, please find attached an > updated patch. My only concern with the internal property approach is > a potential proliferation of similar boolean values if someone else > encounters an incompatibility. Yes they do tend to proliferate. We might drop some down the road after the affected machine type is dropped. > I have not conducted a thorough audit > of all the PIIX 3/4 IDE registers for hardwired bits (only what I > encountered testing proprietary firmware - PCICMD), and I do not have > access to my PIIX 3 system at the moment. > > Kind regards, > Lev Kujawski > > Lev Kujawski (2): > qpci_device_enable: Allow for command bits hardwired to 0 > hw/ide/piix: Ignore writes of hardwired PCI command register bits > > hw/core/machine.c | 5 ++++- > hw/ide/piix.c | 24 ++++++++++++++++++++++++ > include/hw/ide/pci.h | 1 + > tests/qtest/ide-test.c | 1 + > tests/qtest/libqos/pci.c | 13 +++++++------ > tests/qtest/libqos/pci.h | 1 + > 6 files changed, 38 insertions(+), 7 deletions(-) > > -- > 2.34.1