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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: stefanha@redhat.com, "Alex Bennée" <alex.bennee@linaro.org>
Subject: [PULL 15/47] accel/tcg: Introduce tb_{set_}page_addr{0,1}
Date: Wed, 26 Oct 2022 12:10:44 +1000	[thread overview]
Message-ID: <20221026021116.1988449-16-richard.henderson@linaro.org> (raw)
In-Reply-To: <20221026021116.1988449-1-richard.henderson@linaro.org>

This data structure will be replaced for user-only: add accessors.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/exec-all.h   | 22 ++++++++++++++++++++++
 accel/tcg/cpu-exec.c      |  9 +++++----
 accel/tcg/tb-maint.c      | 29 +++++++++++++++--------------
 accel/tcg/translate-all.c | 16 ++++++++--------
 accel/tcg/translator.c    |  9 +++++----
 5 files changed, 55 insertions(+), 30 deletions(-)

diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index b5bde1b56a..5900f4637b 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -610,6 +610,28 @@ static inline uint32_t tb_cflags(const TranslationBlock *tb)
     return qatomic_read(&tb->cflags);
 }
 
+static inline tb_page_addr_t tb_page_addr0(const TranslationBlock *tb)
+{
+    return tb->page_addr[0];
+}
+
+static inline tb_page_addr_t tb_page_addr1(const TranslationBlock *tb)
+{
+    return tb->page_addr[1];
+}
+
+static inline void tb_set_page_addr0(TranslationBlock *tb,
+                                     tb_page_addr_t addr)
+{
+    tb->page_addr[0] = addr;
+}
+
+static inline void tb_set_page_addr1(TranslationBlock *tb,
+                                     tb_page_addr_t addr)
+{
+    tb->page_addr[1] = addr;
+}
+
 /* current cflags for hashing/comparison */
 uint32_t curr_cflags(CPUState *cpu);
 
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index bb4b9e92ce..82b06c1824 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -187,13 +187,14 @@ static bool tb_lookup_cmp(const void *p, const void *d)
     const struct tb_desc *desc = d;
 
     if ((TARGET_TB_PCREL || tb_pc(tb) == desc->pc) &&
-        tb->page_addr[0] == desc->page_addr0 &&
+        tb_page_addr0(tb) == desc->page_addr0 &&
         tb->cs_base == desc->cs_base &&
         tb->flags == desc->flags &&
         tb->trace_vcpu_dstate == desc->trace_vcpu_dstate &&
         tb_cflags(tb) == desc->cflags) {
         /* check next page if needed */
-        if (tb->page_addr[1] == -1) {
+        tb_page_addr_t tb_phys_page1 = tb_page_addr1(tb);
+        if (tb_phys_page1 == -1) {
             return true;
         } else {
             tb_page_addr_t phys_page1;
@@ -210,7 +211,7 @@ static bool tb_lookup_cmp(const void *p, const void *d)
              */
             virt_page1 = TARGET_PAGE_ALIGN(desc->pc);
             phys_page1 = get_page_addr_code(desc->env, virt_page1);
-            if (tb->page_addr[1] == phys_page1) {
+            if (tb_phys_page1 == phys_page1) {
                 return true;
             }
         }
@@ -1019,7 +1020,7 @@ int cpu_exec(CPUState *cpu)
              * direct jump to a TB spanning two pages because the mapping
              * for the second page can change.
              */
-            if (tb->page_addr[1] != -1) {
+            if (tb_page_addr1(tb) != -1) {
                 last_tb = NULL;
             }
 #endif
diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c
index 7f4e1e1299..15ec2f741d 100644
--- a/accel/tcg/tb-maint.c
+++ b/accel/tcg/tb-maint.c
@@ -44,8 +44,8 @@ static bool tb_cmp(const void *ap, const void *bp)
             a->flags == b->flags &&
             (tb_cflags(a) & ~CF_INVALID) == (tb_cflags(b) & ~CF_INVALID) &&
             a->trace_vcpu_dstate == b->trace_vcpu_dstate &&
-            a->page_addr[0] == b->page_addr[0] &&
-            a->page_addr[1] == b->page_addr[1]);
+            tb_page_addr0(a) == tb_page_addr0(b) &&
+            tb_page_addr1(a) == tb_page_addr1(b));
 }
 
 void tb_htable_init(void)
@@ -273,7 +273,7 @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list)
     qemu_spin_unlock(&tb->jmp_lock);
 
     /* remove the TB from the hash list */
-    phys_pc = tb->page_addr[0];
+    phys_pc = tb_page_addr0(tb);
     h = tb_hash_func(phys_pc, (TARGET_TB_PCREL ? 0 : tb_pc(tb)),
                      tb->flags, orig_cflags, tb->trace_vcpu_dstate);
     if (!qht_remove(&tb_ctx.htable, tb, h)) {
@@ -282,10 +282,11 @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list)
 
     /* remove the TB from the page list */
     if (rm_from_page_list) {
-        p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS);
+        p = page_find(phys_pc >> TARGET_PAGE_BITS);
         tb_page_remove(p, tb);
-        if (tb->page_addr[1] != -1) {
-            p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS);
+        phys_pc = tb_page_addr1(tb);
+        if (phys_pc != -1) {
+            p = page_find(phys_pc >> TARGET_PAGE_BITS);
             tb_page_remove(p, tb);
         }
     }
@@ -358,16 +359,16 @@ static inline void page_unlock_tb(const TranslationBlock *tb) { }
 /* lock the page(s) of a TB in the correct acquisition order */
 static void page_lock_tb(const TranslationBlock *tb)
 {
-    page_lock_pair(NULL, tb->page_addr[0], NULL, tb->page_addr[1], false);
+    page_lock_pair(NULL, tb_page_addr0(tb), NULL, tb_page_addr1(tb), false);
 }
 
 static void page_unlock_tb(const TranslationBlock *tb)
 {
-    PageDesc *p1 = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS);
+    PageDesc *p1 = page_find(tb_page_addr0(tb) >> TARGET_PAGE_BITS);
 
     page_unlock(p1);
-    if (unlikely(tb->page_addr[1] != -1)) {
-        PageDesc *p2 = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS);
+    if (unlikely(tb_page_addr1(tb) != -1)) {
+        PageDesc *p2 = page_find(tb_page_addr1(tb) >> TARGET_PAGE_BITS);
 
         if (p2 != p1) {
             page_unlock(p2);
@@ -382,7 +383,7 @@ static void page_unlock_tb(const TranslationBlock *tb)
  */
 void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr)
 {
-    if (page_addr == -1 && tb->page_addr[0] != -1) {
+    if (page_addr == -1 && tb_page_addr0(tb) != -1) {
         page_lock_tb(tb);
         do_tb_phys_invalidate(tb, true);
         page_unlock_tb(tb);
@@ -516,11 +517,11 @@ tb_invalidate_phys_page_range__locked(struct page_collection *pages,
         if (n == 0) {
             /* NOTE: tb_end may be after the end of the page, but
                it is not a problem */
-            tb_start = tb->page_addr[0];
+            tb_start = tb_page_addr0(tb);
             tb_end = tb_start + tb->size;
         } else {
-            tb_start = tb->page_addr[1];
-            tb_end = tb_start + ((tb->page_addr[0] + tb->size)
+            tb_start = tb_page_addr1(tb);
+            tb_end = tb_start + ((tb_page_addr0(tb) + tb->size)
                                  & ~TARGET_PAGE_MASK);
         }
         if (!(tb_end <= start || tb_start >= end)) {
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 5e28e9fccd..bef4c56cff 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -698,9 +698,9 @@ page_collection_lock(tb_page_addr_t start, tb_page_addr_t end)
         }
         assert_page_locked(pd);
         PAGE_FOR_EACH_TB(pd, tb, n) {
-            if (page_trylock_add(set, tb->page_addr[0]) ||
-                (tb->page_addr[1] != -1 &&
-                 page_trylock_add(set, tb->page_addr[1]))) {
+            if (page_trylock_add(set, tb_page_addr0(tb)) ||
+                (tb_page_addr1(tb) != -1 &&
+                 page_trylock_add(set, tb_page_addr1(tb)))) {
                 /* drop all locks, and reacquire in order */
                 g_tree_foreach(set->tree, page_entry_unlock, NULL);
                 goto retry;
@@ -771,8 +771,8 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
     tb->flags = flags;
     tb->cflags = cflags;
     tb->trace_vcpu_dstate = *cpu->trace_dstate;
-    tb->page_addr[0] = phys_pc;
-    tb->page_addr[1] = -1;
+    tb_set_page_addr0(tb, phys_pc);
+    tb_set_page_addr1(tb, -1);
     tcg_ctx->tb_cflags = cflags;
  tb_overflow:
 
@@ -970,7 +970,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
      * a temporary one-insn TB, and we have nothing left to do. Return early
      * before attempting to link to other TBs or add to the lookup table.
      */
-    if (tb->page_addr[0] == -1) {
+    if (tb_page_addr0(tb) == -1) {
         return tb;
     }
 
@@ -985,7 +985,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
      * No explicit memory barrier is required -- tb_link_page() makes the
      * TB visible in a consistent state.
      */
-    existing_tb = tb_link_page(tb, tb->page_addr[0], tb->page_addr[1]);
+    existing_tb = tb_link_page(tb, tb_page_addr0(tb), tb_page_addr1(tb));
     /* if the TB already exists, discard what we just translated */
     if (unlikely(existing_tb != tb)) {
         uintptr_t orig_aligned = (uintptr_t)gen_code_buf;
@@ -1140,7 +1140,7 @@ static gboolean tb_tree_stats_iter(gpointer key, gpointer value, gpointer data)
     if (tb->size > tst->max_target_size) {
         tst->max_target_size = tb->size;
     }
-    if (tb->page_addr[1] != -1) {
+    if (tb_page_addr1(tb) != -1) {
         tst->cross_page++;
     }
     if (tb->jmp_reset_offset[0] != TB_JMP_RESET_OFFSET_INVALID) {
diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
index 8e78fd7a9c..061519691f 100644
--- a/accel/tcg/translator.c
+++ b/accel/tcg/translator.c
@@ -157,7 +157,7 @@ static void *translator_access(CPUArchState *env, DisasContextBase *db,
     tb = db->tb;
 
     /* Use slow path if first page is MMIO. */
-    if (unlikely(tb->page_addr[0] == -1)) {
+    if (unlikely(tb_page_addr0(tb) == -1)) {
         return NULL;
     }
 
@@ -169,13 +169,14 @@ static void *translator_access(CPUArchState *env, DisasContextBase *db,
         host = db->host_addr[1];
         base = TARGET_PAGE_ALIGN(db->pc_first);
         if (host == NULL) {
-            tb->page_addr[1] =
+            tb_page_addr_t phys_page =
                 get_page_addr_code_hostp(env, base, &db->host_addr[1]);
+            /* We cannot handle MMIO as second page. */
+            assert(phys_page != -1);
+            tb_set_page_addr1(tb, phys_page);
 #ifdef CONFIG_USER_ONLY
             page_protect(end);
 #endif
-            /* We cannot handle MMIO as second page. */
-            assert(tb->page_addr[1] != -1);
             host = db->host_addr[1];
         }
 
-- 
2.34.1



  parent reply	other threads:[~2022-10-26  2:14 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-26  2:10 [PULL 00/47] tcg patch queue Richard Henderson
2022-10-26  2:10 ` [PULL 01/47] Revert "accel/tcg: Init TCG cflags in vCPU thread handler" Richard Henderson
2022-10-26  2:10 ` [PULL 02/47] tcg/loongarch64: Add direct jump support Richard Henderson
2022-10-26  2:10 ` [PULL 03/47] tcg/aarch64: Remove unused code in tcg_out_op Richard Henderson
2022-10-26  2:10 ` [PULL 04/47] accel/tcg: Add a quicker check for breakpoints Richard Henderson
2022-10-26  2:10 ` [PULL 05/47] include/qemu/osdep: Add qemu_build_assert Richard Henderson
2022-10-26  2:10 ` [PULL 06/47] include/qemu/atomic: Use qemu_build_assert Richard Henderson
2022-10-26  2:10 ` [PULL 07/47] include/qemu/thread: Use qatomic_* functions Richard Henderson
2022-10-26  2:10 ` [PULL 08/47] accel/tcg: Make page_alloc_target_data allocation constant Richard Henderson
2022-10-26  2:10 ` [PULL 09/47] accel/tcg: Remove disabled debug in translate-all.c Richard Henderson
2022-10-26  2:10 ` [PULL 10/47] accel/tcg: Split out PageDesc to internal.h Richard Henderson
2022-10-26  2:10 ` [PULL 11/47] accel/tcg: Split out tb-maint.c Richard Henderson
2022-10-26  2:10 ` [PULL 12/47] accel/tcg: Move assert_no_pages_locked to internal.h Richard Henderson
2022-10-26  2:10 ` [PULL 13/47] accel/tcg: Drop cpu_get_tb_cpu_state from TARGET_HAS_PRECISE_SMC Richard Henderson
2022-10-26  2:10 ` [PULL 14/47] accel/tcg: Remove duplicate store to tb->page_addr[] Richard Henderson
2022-10-26  2:10 ` Richard Henderson [this message]
2022-10-26  2:10 ` [PULL 16/47] accel/tcg: Rename tb_invalidate_phys_page Richard Henderson
2022-10-26  2:10 ` [PULL 17/47] accel/tcg: Rename tb_invalidate_phys_page_range and drop end parameter Richard Henderson
2022-10-26  2:10 ` [PULL 18/47] accel/tcg: Unify declarations of tb_invalidate_phys_range Richard Henderson
2022-10-26  2:10 ` [PULL 19/47] accel/tcg: Use tb_invalidate_phys_page in page_set_flags Richard Henderson
2022-10-26  2:10 ` [PULL 20/47] accel/tcg: Call tb_invalidate_phys_page for PAGE_RESET Richard Henderson
2022-10-26  2:10 ` [PULL 21/47] accel/tcg: Use page_reset_target_data in page_set_flags Richard Henderson
2022-10-26  2:10 ` [PULL 22/47] accel/tcg: Use tb_invalidate_phys_range " Richard Henderson
2022-10-26  2:10 ` [PULL 23/47] accel/tcg: Move TARGET_PAGE_DATA_SIZE impl to user-exec.c Richard Henderson
2022-10-26  2:10 ` [PULL 24/47] accel/tcg: Simplify page_get/alloc_target_data Richard Henderson
2022-10-26  2:10 ` [PULL 25/47] accel/tcg: Add restore_state_to_opc to TCGCPUOps Richard Henderson
2022-10-29 10:42   ` Alex Bennée
2022-10-31  0:10     ` Richard Henderson
2022-10-31 17:56   ` Christian Schoenebeck
2022-10-31 20:35     ` Richard Henderson
2022-10-31 20:53       ` Stefan Hajnoczi
2022-10-31 21:27         ` Mark Cave-Ayland
2022-10-31 22:03           ` Richard Henderson
2022-10-26  2:10 ` [PULL 26/47] target/alpha: Convert to tcg_ops restore_state_to_opc Richard Henderson
2022-10-26  2:10 ` [PULL 27/47] target/arm: " Richard Henderson
2022-10-26  2:10 ` [PULL 28/47] target/avr: " Richard Henderson
2022-10-26  2:10 ` [PULL 29/47] target/cris: " Richard Henderson
2022-10-26  2:10 ` [PULL 30/47] target/hexagon: " Richard Henderson
2022-10-26  2:11 ` [PULL 31/47] target/hppa: " Richard Henderson
2022-10-26  2:11 ` [PULL 32/47] target/i386: " Richard Henderson
2022-10-26  2:11 ` [PULL 33/47] target/loongarch: " Richard Henderson
2022-10-26  2:11 ` [PULL 34/47] target/m68k: " Richard Henderson
2022-10-26  2:11 ` [PULL 35/47] target/microblaze: " Richard Henderson
2022-10-26  2:11 ` [PULL 36/47] target/mips: " Richard Henderson
2022-10-26  2:11 ` [PULL 37/47] target/nios2: " Richard Henderson
2022-10-26  2:11 ` [PULL 38/47] target/openrisc: " Richard Henderson
2022-10-26  2:11 ` [PULL 39/47] target/ppc: " Richard Henderson
2022-10-26  2:11 ` [PULL 40/47] target/riscv: " Richard Henderson
2022-10-26  2:11 ` [PULL 41/47] target/rx: " Richard Henderson
2022-10-26  2:11 ` [PULL 42/47] target/s390x: " Richard Henderson
2022-10-26  2:11 ` [PULL 43/47] target/sh4: " Richard Henderson
2022-10-26  2:11 ` [PULL 44/47] target/sparc: " Richard Henderson
2022-10-26  2:11 ` [PULL 45/47] target/tricore: " Richard Henderson
2022-10-26  2:11 ` [PULL 46/47] target/xtensa: " Richard Henderson
2022-10-26  2:11 ` [PULL 47/47] accel/tcg: Remove restore_state_to_opc function Richard Henderson
2022-10-26 18:54 ` [PULL 00/47] tcg patch queue Stefan Hajnoczi

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