From: "Michael S. Tsirkin" <mst@redhat.com>
To: Gregory Price <gregory.price@memverge.com>
Cc: Gregory Price <gourry.memverge@gmail.com>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"jonathan.cameron@huawei.com" <jonathan.cameron@huawei.com>,
"linux-cxl@vger.kernel.org" <linux-cxl@vger.kernel.org>,
"alison.schofield@intel.com" <alison.schofield@intel.com>,
"dave@stgolabs.net" <dave@stgolabs.net>,
"a.manzanares@samsung.com" <a.manzanares@samsung.com>,
"bwidawsk@kernel.org" <bwidawsk@kernel.org>
Subject: Re: [PATCH 1/2] hw/cxl: set cxl-type3 device type to PCI_CLASS_MEMORY_CXL
Date: Wed, 26 Oct 2022 16:11:29 -0400 [thread overview]
Message-ID: <20221026161044-mutt-send-email-mst@kernel.org> (raw)
In-Reply-To: <BN6PR17MB312197C4CA958ED267BB576683309@BN6PR17MB3121.namprd17.prod.outlook.com>
He does but in the end he sends patches not pull requests.
I don't care really as long as someone will send it up.
On Wed, Oct 26, 2022 at 08:09:45PM +0000, Gregory Price wrote:
> I believe this was dropped from my line because Jonathan carried a similar commit on his branch.
>
> Happy to push it up again as a separate commit if that is what you want.
>
> Noted for the future on upstreams
>
> -----Original Message-----
> From: Michael S. Tsirkin <mst@redhat.com>
> Sent: Wednesday, October 26, 2022 4:06 PM
> To: Gregory Price <gourry.memverge@gmail.com>
> Cc: qemu-devel@nongnu.org; jonathan.cameron@huawei.com; linux-cxl@vger.kernel.org; alison.schofield@intel.com; dave@stgolabs.net; a.manzanares@samsung.com; bwidawsk@kernel.org; Gregory Price <gregory.price@memverge.com>
> Subject: Re: [PATCH 1/2] hw/cxl: set cxl-type3 device type to PCI_CLASS_MEMORY_CXL
>
> On Thu, Oct 06, 2022 at 07:37:01PM -0400, Gregory Price wrote:
> > Current code sets to STORAGE_EXPRESS and then overrides it.
> >
> > Signed-off-by: Gregory Price <gregory.price@memverge.com>
>
> If you expect me to merge it you need to CC me.
> Also, do we need this separately from the series?
>
> > ---
> > hw/mem/cxl_type3.c | 3 +--
> > 1 file changed, 1 insertion(+), 2 deletions(-)
> >
> > diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index
> > ada2108fac..1837c1c83a 100644
> > --- a/hw/mem/cxl_type3.c
> > +++ b/hw/mem/cxl_type3.c
> > @@ -146,7 +146,6 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp)
> > }
> >
> > pci_config_set_prog_interface(pci_conf, 0x10);
> > - pci_config_set_class(pci_conf, PCI_CLASS_MEMORY_CXL);
> >
> > pcie_endpoint_cap_init(pci_dev, 0x80);
> > cxl_cstate->dvsec_offset = 0x100; @@ -335,7 +334,7 @@ static void
> > ct3_class_init(ObjectClass *oc, void *data)
> >
> > pc->realize = ct3_realize;
> > pc->exit = ct3_exit;
> > - pc->class_id = PCI_CLASS_STORAGE_EXPRESS;
> > + pc->class_id = PCI_CLASS_MEMORY_CXL;
> > pc->vendor_id = PCI_VENDOR_ID_INTEL;
> > pc->device_id = 0xd93; /* LVF for now */
> > pc->revision = 1;
> > --
> > 2.37.3
> >
> >
next prev parent reply other threads:[~2022-10-26 20:14 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-06 23:37 [PATCH 1/2] hw/cxl: set cxl-type3 device type to PCI_CLASS_MEMORY_CXL Gregory Price
2022-10-06 23:37 ` [PATCH 2/2] hw/cxl: Allow CXL type-3 devices to be persistent or volatile Gregory Price
2022-10-10 15:25 ` Jonathan Cameron via
2022-10-10 17:12 ` Davidlohr Bueso
2022-10-10 19:36 ` Davidlohr Bueso
2022-10-10 20:07 ` Gregory Price
2022-10-07 16:35 ` [PATCH 1/2] hw/cxl: set cxl-type3 device type to PCI_CLASS_MEMORY_CXL Jonathan Cameron via
2022-10-07 17:10 ` Davidlohr Bueso
2022-10-07 17:16 ` Davidlohr Bueso
2022-10-26 20:06 ` Michael S. Tsirkin
2022-10-26 20:09 ` Gregory Price
2022-10-26 20:11 ` Michael S. Tsirkin [this message]
2022-10-26 21:07 ` Gregory Price
2022-11-03 18:12 ` Jonathan Cameron via
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