* [PATCH v4 1/3] hw/mips/bootloader: Allow bl_gen_jump_kernel to optionally set register
2022-10-26 19:18 [PATCH v4 0/3] MIPS Bootloader helper Philippe Mathieu-Daudé
@ 2022-10-26 19:18 ` Philippe Mathieu-Daudé
2022-10-26 19:18 ` [PATCH v4 2/3] hw/mips: Use bl_gen_kernel_jump to generate bootloaders Philippe Mathieu-Daudé
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Philippe Mathieu-Daudé @ 2022-10-26 19:18 UTC (permalink / raw)
To: qemu-devel
Cc: Aurelien Jarno, Paul Burton, Jiaxun Yang, Huacai Chen,
Philippe Mathieu-Daudé, Aleksandar Rikalo
When one of the $sp/$a[0..3] register is already set, we might
want bl_gen_jump_kernel() to NOT set it again. Pass a boolean
argument for each register, to allow to optionally set them.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/mips/bootloader.c | 28 +++++++++++++++++++++-------
hw/mips/boston.c | 5 ++++-
hw/mips/fuloong2e.c | 8 ++++++--
include/hw/mips/bootloader.h | 8 ++++++--
4 files changed, 37 insertions(+), 12 deletions(-)
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index 99991f8b2b..f5f42f2bf2 100644
--- a/hw/mips/bootloader.c
+++ b/hw/mips/bootloader.c
@@ -165,15 +165,29 @@ void bl_gen_jump_to(uint32_t **p, target_ulong jump_addr)
bl_gen_nop(p); /* delay slot */
}
-void bl_gen_jump_kernel(uint32_t **p, target_ulong sp, target_ulong a0,
- target_ulong a1, target_ulong a2, target_ulong a3,
+void bl_gen_jump_kernel(uint32_t **p,
+ bool set_sp, target_ulong sp,
+ bool set_a0, target_ulong a0,
+ bool set_a1, target_ulong a1,
+ bool set_a2, target_ulong a2,
+ bool set_a3, target_ulong a3,
target_ulong kernel_addr)
{
- bl_gen_load_ulong(p, BL_REG_SP, sp);
- bl_gen_load_ulong(p, BL_REG_A0, a0);
- bl_gen_load_ulong(p, BL_REG_A1, a1);
- bl_gen_load_ulong(p, BL_REG_A2, a2);
- bl_gen_load_ulong(p, BL_REG_A3, a3);
+ if (set_sp) {
+ bl_gen_load_ulong(p, BL_REG_SP, sp);
+ }
+ if (set_a0) {
+ bl_gen_load_ulong(p, BL_REG_A0, a0);
+ }
+ if (set_a1) {
+ bl_gen_load_ulong(p, BL_REG_A1, a1);
+ }
+ if (set_a2) {
+ bl_gen_load_ulong(p, BL_REG_A2, a2);
+ }
+ if (set_a3) {
+ bl_gen_load_ulong(p, BL_REG_A3, a3);
+ }
bl_gen_jump_to(p, kernel_addr);
}
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index d2ab9da1a0..8976f036e6 100644
--- a/hw/mips/boston.c
+++ b/hw/mips/boston.c
@@ -351,7 +351,10 @@ static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr)
* a2/$6 = 0
* a3/$7 = 0
*/
- bl_gen_jump_kernel(&p, 0, (int32_t)-2, fdt_addr, 0, 0, kernel_entry);
+ bl_gen_jump_kernel(&p,
+ true, 0, true, (int32_t)-2,
+ true, fdt_addr, true, 0, true, 0,
+ kernel_entry);
}
static const void *boston_fdt_filter(void *opaque, const void *fdt_orig,
diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c
index 5ee546f5f6..b7bf48f9b8 100644
--- a/hw/mips/fuloong2e.c
+++ b/hw/mips/fuloong2e.c
@@ -180,8 +180,12 @@ static void write_bootloader(CPUMIPSState *env, uint8_t *base,
/* Second part of the bootloader */
p = (uint32_t *)(base + 0x040);
- bl_gen_jump_kernel(&p, ENVP_VADDR - 64, 2, ENVP_VADDR, ENVP_VADDR + 8,
- loaderparams.ram_size, kernel_addr);
+ bl_gen_jump_kernel(&p,
+ true, ENVP_VADDR - 64,
+ true, 2, true, ENVP_VADDR,
+ true, ENVP_VADDR + 8,
+ true, loaderparams.ram_size,
+ kernel_addr);
}
static void main_cpu_reset(void *opaque)
diff --git a/include/hw/mips/bootloader.h b/include/hw/mips/bootloader.h
index b5f48d71bb..fffb0b7da8 100644
--- a/include/hw/mips/bootloader.h
+++ b/include/hw/mips/bootloader.h
@@ -12,8 +12,12 @@
#include "exec/cpu-defs.h"
void bl_gen_jump_to(uint32_t **p, target_ulong jump_addr);
-void bl_gen_jump_kernel(uint32_t **p, target_ulong sp, target_ulong a0,
- target_ulong a1, target_ulong a2, target_ulong a3,
+void bl_gen_jump_kernel(uint32_t **p,
+ bool set_sp, target_ulong sp,
+ bool set_a0, target_ulong a0,
+ bool set_a1, target_ulong a1,
+ bool set_a2, target_ulong a2,
+ bool set_a3, target_ulong a3,
target_ulong kernel_addr);
void bl_gen_write_ulong(uint32_t **p, target_ulong addr, target_ulong val);
void bl_gen_write_u32(uint32_t **p, target_ulong addr, uint32_t val);
--
2.37.3
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH v4 2/3] hw/mips: Use bl_gen_kernel_jump to generate bootloaders
2022-10-26 19:18 [PATCH v4 0/3] MIPS Bootloader helper Philippe Mathieu-Daudé
2022-10-26 19:18 ` [PATCH v4 1/3] hw/mips/bootloader: Allow bl_gen_jump_kernel to optionally set register Philippe Mathieu-Daudé
@ 2022-10-26 19:18 ` Philippe Mathieu-Daudé
2022-10-26 19:18 ` [PATCH v4 3/3] hw/mips/malta: Use bootloader helper to set BAR registers Philippe Mathieu-Daudé
2022-10-27 10:35 ` [PATCH v4 0/3] MIPS Bootloader helper Jiaxun Yang
3 siblings, 0 replies; 5+ messages in thread
From: Philippe Mathieu-Daudé @ 2022-10-26 19:18 UTC (permalink / raw)
To: qemu-devel
Cc: Aurelien Jarno, Paul Burton, Jiaxun Yang, Huacai Chen,
Philippe Mathieu-Daudé, Aleksandar Rikalo
From: Jiaxun Yang <jiaxun.yang@flygoat.com>
Replace embedded binary with generated code.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20210127065424.114125-3-jiaxun.yang@flygoat.com>
[PMD: Pass semihosting_get_argc() to bl_gen_jump_kernel()]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/mips/malta.c | 43 ++++++++++++-------------------------------
1 file changed, 12 insertions(+), 31 deletions(-)
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 0e932988e0..e24572c885 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -35,6 +35,7 @@
#include "hw/i2c/smbus_eeprom.h"
#include "hw/block/flash.h"
#include "hw/mips/mips.h"
+#include "hw/mips/bootloader.h"
#include "hw/mips/cpudevs.h"
#include "hw/pci/pci.h"
#include "qemu/log.h"
@@ -866,30 +867,6 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr,
/* Second part of the bootloader */
p = (uint32_t *) (base + 0x580);
- if (semihosting_get_argc()) {
- /* Preserve a0 content as arguments have been passed */
- stl_p(p++, 0x00000000); /* nop */
- } else {
- stl_p(p++, 0x24040002); /* addiu a0, zero, 2 */
- }
-
- /* lui sp, high(ENVP_VADDR) */
- stl_p(p++, 0x3c1d0000 | (((ENVP_VADDR - 64) >> 16) & 0xffff));
- /* ori sp, sp, low(ENVP_VADDR) */
- stl_p(p++, 0x37bd0000 | ((ENVP_VADDR - 64) & 0xffff));
- /* lui a1, high(ENVP_VADDR) */
- stl_p(p++, 0x3c050000 | ((ENVP_VADDR >> 16) & 0xffff));
- /* ori a1, a1, low(ENVP_VADDR) */
- stl_p(p++, 0x34a50000 | (ENVP_VADDR & 0xffff));
- /* lui a2, high(ENVP_VADDR + 8) */
- stl_p(p++, 0x3c060000 | (((ENVP_VADDR + 8) >> 16) & 0xffff));
- /* ori a2, a2, low(ENVP_VADDR + 8) */
- stl_p(p++, 0x34c60000 | ((ENVP_VADDR + 8) & 0xffff));
- /* lui a3, high(ram_low_size) */
- stl_p(p++, 0x3c070000 | (loaderparams.ram_low_size >> 16));
- /* ori a3, a3, low(ram_low_size) */
- stl_p(p++, 0x34e70000 | (loaderparams.ram_low_size & 0xffff));
-
/* Load BAR registers as done by YAMON */
stl_p(p++, 0x3c09b400); /* lui t1, 0xb400 */
@@ -941,13 +918,17 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr,
#endif
stl_p(p++, 0xad280088); /* sw t0, 0x0088(t1) */
- /* Jump to kernel code */
- stl_p(p++, 0x3c1f0000 |
- ((kernel_entry >> 16) & 0xffff)); /* lui ra, high(kernel_entry) */
- stl_p(p++, 0x37ff0000 |
- (kernel_entry & 0xffff)); /* ori ra, ra, low(kernel_entry) */
- stl_p(p++, 0x03e00009); /* jalr ra */
- stl_p(p++, 0x00000000); /* nop */
+ bl_gen_jump_kernel(&p,
+ true, ENVP_VADDR - 64,
+ /*
+ * If semihosting is used, arguments have already been
+ * passed, so we preserve $a0.
+ */
+ !semihosting_get_argc(), 2,
+ true, ENVP_VADDR,
+ true, ENVP_VADDR + 8,
+ true, loaderparams.ram_low_size,
+ kernel_entry);
/* YAMON subroutines */
p = (uint32_t *) (base + 0x800);
--
2.37.3
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH v4 3/3] hw/mips/malta: Use bootloader helper to set BAR registers
2022-10-26 19:18 [PATCH v4 0/3] MIPS Bootloader helper Philippe Mathieu-Daudé
2022-10-26 19:18 ` [PATCH v4 1/3] hw/mips/bootloader: Allow bl_gen_jump_kernel to optionally set register Philippe Mathieu-Daudé
2022-10-26 19:18 ` [PATCH v4 2/3] hw/mips: Use bl_gen_kernel_jump to generate bootloaders Philippe Mathieu-Daudé
@ 2022-10-26 19:18 ` Philippe Mathieu-Daudé
2022-10-27 10:35 ` [PATCH v4 0/3] MIPS Bootloader helper Jiaxun Yang
3 siblings, 0 replies; 5+ messages in thread
From: Philippe Mathieu-Daudé @ 2022-10-26 19:18 UTC (permalink / raw)
To: qemu-devel
Cc: Aurelien Jarno, Paul Burton, Jiaxun Yang, Huacai Chen,
Philippe Mathieu-Daudé, Aleksandar Rikalo
From: Jiaxun Yang <jiaxun.yang@flygoat.com>
Translate embedded assembly into IO writes which is more
readable.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20210127065424.114125-4-jiaxun.yang@flygoat.com>
[PMD: Explode addresses/values to ease review/maintainance]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/mips/malta.c | 79 +++++++++++++++++++++++--------------------------
1 file changed, 37 insertions(+), 42 deletions(-)
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index e24572c885..272d93eea7 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -867,56 +867,51 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr,
/* Second part of the bootloader */
p = (uint32_t *) (base + 0x580);
- /* Load BAR registers as done by YAMON */
- stl_p(p++, 0x3c09b400); /* lui t1, 0xb400 */
+ /*
+ * Load BAR registers as done by YAMON:
+ *
+ * - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff
+ * - set up PCI0 MEM0 at 0x10000000, size 0x7e00000
+ * - set up PCI0 MEM1 at 0x18200000, size 0xbc00000
+ *
+ */
+ /* Bus endianess is always reversed */
#if TARGET_BIG_ENDIAN
- stl_p(p++, 0x3c08df00); /* lui t0, 0xdf00 */
+#define cpu_to_gt32 cpu_to_le32
#else
- stl_p(p++, 0x340800df); /* ori t0, r0, 0x00df */
+#define cpu_to_gt32 cpu_to_be32
#endif
- stl_p(p++, 0xad280068); /* sw t0, 0x0068(t1) */
- stl_p(p++, 0x3c09bbe0); /* lui t1, 0xbbe0 */
+ /* move GT64120 registers from 0x14000000 to 0x1be00000 */
+ bl_gen_write_u32(&p, /* GT_ISD */
+ cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68),
+ cpu_to_gt32(0x1be00000 << 3));
-#if TARGET_BIG_ENDIAN
- stl_p(p++, 0x3c08c000); /* lui t0, 0xc000 */
-#else
- stl_p(p++, 0x340800c0); /* ori t0, r0, 0x00c0 */
-#endif
- stl_p(p++, 0xad280048); /* sw t0, 0x0048(t1) */
-#if TARGET_BIG_ENDIAN
- stl_p(p++, 0x3c084000); /* lui t0, 0x4000 */
-#else
- stl_p(p++, 0x34080040); /* ori t0, r0, 0x0040 */
-#endif
- stl_p(p++, 0xad280050); /* sw t0, 0x0050(t1) */
+ /* setup MEM-to-PCI0 mapping */
+ /* setup PCI0 io window to 0x18000000-0x181fffff */
+ bl_gen_write_u32(&p, /* GT_PCI0IOLD */
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48),
+ cpu_to_gt32(0x18000000 << 3));
+ bl_gen_write_u32(&p, /* GT_PCI0IOHD */
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50),
+ cpu_to_gt32(0x08000000 << 3));
+ /* setup PCI0 mem windows */
+ bl_gen_write_u32(&p, /* GT_PCI0M0LD */
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),
+ cpu_to_gt32(0x10000000 << 3));
+ bl_gen_write_u32(&p, /* GT_PCI0M0HD */
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60),
+ cpu_to_gt32(0x07e00000 << 3));
-#if TARGET_BIG_ENDIAN
- stl_p(p++, 0x3c088000); /* lui t0, 0x8000 */
-#else
- stl_p(p++, 0x34080080); /* ori t0, r0, 0x0080 */
-#endif
- stl_p(p++, 0xad280058); /* sw t0, 0x0058(t1) */
-#if TARGET_BIG_ENDIAN
- stl_p(p++, 0x3c083f00); /* lui t0, 0x3f00 */
-#else
- stl_p(p++, 0x3408003f); /* ori t0, r0, 0x003f */
-#endif
- stl_p(p++, 0xad280060); /* sw t0, 0x0060(t1) */
+ bl_gen_write_u32(&p, /* GT_PCI0M1LD */
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80),
+ cpu_to_gt32(0x18200000 << 3));
+ bl_gen_write_u32(&p, /* GT_PCI0M1HD */
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88),
+ cpu_to_gt32(0x0bc00000 << 3));
-#if TARGET_BIG_ENDIAN
- stl_p(p++, 0x3c08c100); /* lui t0, 0xc100 */
-#else
- stl_p(p++, 0x340800c1); /* ori t0, r0, 0x00c1 */
-#endif
- stl_p(p++, 0xad280080); /* sw t0, 0x0080(t1) */
-#if TARGET_BIG_ENDIAN
- stl_p(p++, 0x3c085e00); /* lui t0, 0x5e00 */
-#else
- stl_p(p++, 0x3408005e); /* ori t0, r0, 0x005e */
-#endif
- stl_p(p++, 0xad280088); /* sw t0, 0x0088(t1) */
+#undef cpu_to_gt32
bl_gen_jump_kernel(&p,
true, ENVP_VADDR - 64,
--
2.37.3
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH v4 0/3] MIPS Bootloader helper
2022-10-26 19:18 [PATCH v4 0/3] MIPS Bootloader helper Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2022-10-26 19:18 ` [PATCH v4 3/3] hw/mips/malta: Use bootloader helper to set BAR registers Philippe Mathieu-Daudé
@ 2022-10-27 10:35 ` Jiaxun Yang
3 siblings, 0 replies; 5+ messages in thread
From: Jiaxun Yang @ 2022-10-27 10:35 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Aurelien Jarno, Paul Burton, Huacai Chen,
Aleksandar Rikalo
> 2022年10月26日 20:18，Philippe Mathieu-Daudé <philmd@linaro.org> 写道：
>
> This is a respin of Jiaxun v3 [1] addressing the semihosting review
> comment [2].
>
> [1] https://lore.kernel.org/qemu-devel/20210127065424.114125-1-jiaxun.yang@flygoat.com/
> [2] https://lore.kernel.org/qemu-devel/5a22bbe1-5023-6fc3-a41b-8d72ec2bb4a1@flygoat.com/
For the series:
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Jiaxun Yang <jiaxun,yang@flygoat.com>
I thought this series was committed in whole.. Just forgot that there are still something remaining :-)
Thanks
- Jiaxun
>
> *** BLURB HERE ***
>
> Jiaxun Yang (2):
> hw/mips: Use bl_gen_kernel_jump to generate bootloaders
> hw/mips/malta: Use bootloader helper to set BAR registers
>
> Philippe Mathieu-Daudé (1):
> hw/mips/bootloader: Allow bl_gen_jump_kernel to optionally set
> register
>
> hw/mips/bootloader.c | 28 ++++++--
> hw/mips/boston.c | 5 +-
> hw/mips/fuloong2e.c | 8 ++-
> hw/mips/malta.c | 122 ++++++++++++++---------------------
> include/hw/mips/bootloader.h | 8 ++-
> 5 files changed, 86 insertions(+), 85 deletions(-)
>
> --
> 2.37.3
>
---
Jiaxun Yang
^ permalink raw reply [flat|nested] 5+ messages in thread