From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Aurelien Jarno" <aurelien@aurel32.net>,
"Paul Burton" <paulburton@kernel.org>,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"Huacai Chen" <chenhuacai@kernel.org>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>
Subject: [PATCH v4 3/3] hw/mips/malta: Use bootloader helper to set BAR registers
Date: Wed, 26 Oct 2022 21:18:21 +0200 [thread overview]
Message-ID: <20221026191821.28167-4-philmd@linaro.org> (raw)
In-Reply-To: <20221026191821.28167-1-philmd@linaro.org>
From: Jiaxun Yang <jiaxun.yang@flygoat.com>
Translate embedded assembly into IO writes which is more
readable.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20210127065424.114125-4-jiaxun.yang@flygoat.com>
[PMD: Explode addresses/values to ease review/maintainance]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/mips/malta.c | 79 +++++++++++++++++++++++--------------------------
1 file changed, 37 insertions(+), 42 deletions(-)
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index e24572c885..272d93eea7 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -867,56 +867,51 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr,
/* Second part of the bootloader */
p = (uint32_t *) (base + 0x580);
- /* Load BAR registers as done by YAMON */
- stl_p(p++, 0x3c09b400); /* lui t1, 0xb400 */
+ /*
+ * Load BAR registers as done by YAMON:
+ *
+ * - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff
+ * - set up PCI0 MEM0 at 0x10000000, size 0x7e00000
+ * - set up PCI0 MEM1 at 0x18200000, size 0xbc00000
+ *
+ */
+ /* Bus endianess is always reversed */
#if TARGET_BIG_ENDIAN
- stl_p(p++, 0x3c08df00); /* lui t0, 0xdf00 */
+#define cpu_to_gt32 cpu_to_le32
#else
- stl_p(p++, 0x340800df); /* ori t0, r0, 0x00df */
+#define cpu_to_gt32 cpu_to_be32
#endif
- stl_p(p++, 0xad280068); /* sw t0, 0x0068(t1) */
- stl_p(p++, 0x3c09bbe0); /* lui t1, 0xbbe0 */
+ /* move GT64120 registers from 0x14000000 to 0x1be00000 */
+ bl_gen_write_u32(&p, /* GT_ISD */
+ cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68),
+ cpu_to_gt32(0x1be00000 << 3));
-#if TARGET_BIG_ENDIAN
- stl_p(p++, 0x3c08c000); /* lui t0, 0xc000 */
-#else
- stl_p(p++, 0x340800c0); /* ori t0, r0, 0x00c0 */
-#endif
- stl_p(p++, 0xad280048); /* sw t0, 0x0048(t1) */
-#if TARGET_BIG_ENDIAN
- stl_p(p++, 0x3c084000); /* lui t0, 0x4000 */
-#else
- stl_p(p++, 0x34080040); /* ori t0, r0, 0x0040 */
-#endif
- stl_p(p++, 0xad280050); /* sw t0, 0x0050(t1) */
+ /* setup MEM-to-PCI0 mapping */
+ /* setup PCI0 io window to 0x18000000-0x181fffff */
+ bl_gen_write_u32(&p, /* GT_PCI0IOLD */
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48),
+ cpu_to_gt32(0x18000000 << 3));
+ bl_gen_write_u32(&p, /* GT_PCI0IOHD */
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50),
+ cpu_to_gt32(0x08000000 << 3));
+ /* setup PCI0 mem windows */
+ bl_gen_write_u32(&p, /* GT_PCI0M0LD */
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),
+ cpu_to_gt32(0x10000000 << 3));
+ bl_gen_write_u32(&p, /* GT_PCI0M0HD */
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60),
+ cpu_to_gt32(0x07e00000 << 3));
-#if TARGET_BIG_ENDIAN
- stl_p(p++, 0x3c088000); /* lui t0, 0x8000 */
-#else
- stl_p(p++, 0x34080080); /* ori t0, r0, 0x0080 */
-#endif
- stl_p(p++, 0xad280058); /* sw t0, 0x0058(t1) */
-#if TARGET_BIG_ENDIAN
- stl_p(p++, 0x3c083f00); /* lui t0, 0x3f00 */
-#else
- stl_p(p++, 0x3408003f); /* ori t0, r0, 0x003f */
-#endif
- stl_p(p++, 0xad280060); /* sw t0, 0x0060(t1) */
+ bl_gen_write_u32(&p, /* GT_PCI0M1LD */
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80),
+ cpu_to_gt32(0x18200000 << 3));
+ bl_gen_write_u32(&p, /* GT_PCI0M1HD */
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88),
+ cpu_to_gt32(0x0bc00000 << 3));
-#if TARGET_BIG_ENDIAN
- stl_p(p++, 0x3c08c100); /* lui t0, 0xc100 */
-#else
- stl_p(p++, 0x340800c1); /* ori t0, r0, 0x00c1 */
-#endif
- stl_p(p++, 0xad280080); /* sw t0, 0x0080(t1) */
-#if TARGET_BIG_ENDIAN
- stl_p(p++, 0x3c085e00); /* lui t0, 0x5e00 */
-#else
- stl_p(p++, 0x3408005e); /* ori t0, r0, 0x005e */
-#endif
- stl_p(p++, 0xad280088); /* sw t0, 0x0088(t1) */
+#undef cpu_to_gt32
bl_gen_jump_kernel(&p,
true, ENVP_VADDR - 64,
--
2.37.3
next prev parent reply other threads:[~2022-10-26 19:25 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-26 19:18 [PATCH v4 0/3] MIPS Bootloader helper Philippe Mathieu-Daudé
2022-10-26 19:18 ` [PATCH v4 1/3] hw/mips/bootloader: Allow bl_gen_jump_kernel to optionally set register Philippe Mathieu-Daudé
2022-10-26 19:18 ` [PATCH v4 2/3] hw/mips: Use bl_gen_kernel_jump to generate bootloaders Philippe Mathieu-Daudé
2022-10-26 19:18 ` Philippe Mathieu-Daudé [this message]
2022-10-27 10:35 ` [PATCH v4 0/3] MIPS Bootloader helper Jiaxun Yang
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