qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Bernhard Beschow <shentey@gmail.com>, qemu-devel@nongnu.org
Cc: "Jiaxun Yang" <jiaxun.yang@flygoat.com>,
	"Hervé Poussineau" <hpoussin@reactos.org>,
	"Aurelien Jarno" <aurelien@aurel32.net>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH 3/3] hw/isa/piix4: Correct IRQRC[A:D] reset values
Date: Wed, 26 Oct 2022 21:46:19 +0200	[thread overview]
Message-ID: <20221026194619.28880-4-philmd@linaro.org> (raw)
In-Reply-To: <20221026194619.28880-1-philmd@linaro.org>

IRQRC[A:D] registers reset value is 0x80. We were forcing
the MIPS Malta machine routing to be able to boot a Linux
kernel without any bootloader.
We now have these registers initialized in the Malta machine
write_bootloader(), so we can use the correct reset values.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/isa/piix4.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 15f344dbb7..a2165c6a49 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -115,10 +115,10 @@ static void piix4_isa_reset(DeviceState *dev)
     pci_conf[0x4c] = 0x4d;
     pci_conf[0x4e] = 0x03;
     pci_conf[0x4f] = 0x00;
-    pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10
-    pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10
-    pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11
-    pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11
+    pci_conf[0x60] = 0x80;
+    pci_conf[0x61] = 0x80;
+    pci_conf[0x62] = 0x80;
+    pci_conf[0x63] = 0x80;
     pci_conf[0x69] = 0x02;
     pci_conf[0x70] = 0x80;
     pci_conf[0x76] = 0x0c;
-- 
2.37.3



  parent reply	other threads:[~2022-10-26 19:50 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-26 19:46 [PATCH 0/3] hw/isa/piix4: Remove MIPS Malta specific bits Philippe Mathieu-Daudé
2022-10-26 19:46 ` [PATCH 1/3] hw/mips/malta: Introduce PIIX4_PCI_DEVFN definition Philippe Mathieu-Daudé
2022-10-26 19:46 ` [PATCH 2/3] hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader Philippe Mathieu-Daudé
2022-10-26 19:46 ` Philippe Mathieu-Daudé [this message]
2022-10-26 21:32   ` [PATCH 3/3] hw/isa/piix4: Correct IRQRC[A:D] reset values Bernhard Beschow
2022-10-27 20:45     ` Philippe Mathieu-Daudé
2022-10-26 19:48 ` [PATCH 0/3] hw/isa/piix4: Remove MIPS Malta specific bits Philippe Mathieu-Daudé

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20221026194619.28880-4-philmd@linaro.org \
    --to=philmd@linaro.org \
    --cc=aurelien@aurel32.net \
    --cc=hpoussin@reactos.org \
    --cc=jiaxun.yang@flygoat.com \
    --cc=qemu-devel@nongnu.org \
    --cc=shentey@gmail.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).