From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: Jerome Forissier <jerome.forissier@linaro.org>
Subject: [PATCH 2/2] hw/arm/boot: Set SCR_EL3.HXEn when booting kernel
Date: Thu, 27 Oct 2022 15:02:07 +0100 [thread overview]
Message-ID: <20221027140207.413084-3-peter.maydell@linaro.org> (raw)
In-Reply-To: <20221027140207.413084-1-peter.maydell@linaro.org>
When we direct boot a kernel on a CPU which emulates EL3, we need to
set up the EL3 system registers as the Linux kernel documentation
specifies:
https://www.kernel.org/doc/Documentation/arm64/booting.rst
For CPUs with FEAT_HCX support this includes:
- SCR_EL3.HXEn (bit 38) must be initialised to 0b1.
but we forgot to do this when implementing FEAT_HCX, which would mean
that a guest trying to access the HCRX_EL2 register would crash.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/boot.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 0e4d1e5a816..ddb7b1bdba0 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -769,6 +769,9 @@ static void do_cpu_reset(void *opaque)
env->cp15.scr_el3 |= SCR_ENTP2;
env->vfp.smcr_el[3] = 0xf;
}
+ if (cpu_isar_feature(aa64_hcx, cpu)) {
+ env->cp15.scr_el3 |= SCR_HXEN;
+ }
/* AArch64 kernels never boot in secure mode */
assert(!info->secure_boot);
/* This hook is only supported for AArch32 currently:
--
2.25.1
next prev parent reply other threads:[~2022-10-27 14:04 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-27 14:02 [PATCH 0/2] hw/arm/boot.c: Set EL3 HXen, vector lengths when direct booting kernel Peter Maydell
2022-10-27 14:02 ` [PATCH 1/2] hw/arm/boot: Set SME and SVE EL3 vector lengths when " Peter Maydell
2022-10-27 20:22 ` Richard Henderson
2022-10-27 14:02 ` Peter Maydell [this message]
2022-10-27 20:23 ` [PATCH 2/2] hw/arm/boot: Set SCR_EL3.HXEn " Richard Henderson
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