From: Anup Patel <apatel@ventanamicro.com>
To: Peter Maydell <peter.maydell@linaro.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Atish Patra <atishp@atishpatra.org>,
Richard Henderson <richard.henderson@linaro.org>,
Anup Patel <anup@brainfault.org>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH 0/5] Nested virtualization fixes for QEMU
Date: Thu, 27 Oct 2022 22:17:38 +0530 [thread overview]
Message-ID: <20221027164743.194265-1-apatel@ventanamicro.com> (raw)
This series mainly includes fixes discovered while developing nested
virtualization running on QEMU.
These patches can also be found in the riscv_nested_fixes_v1 branch at:
https://github.com/avpatel/qemu.git
Anup Patel (5):
target/riscv: Typo fix in sstc() predicate
target/riscv: Update VS timer whenever htimedelta changes
target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP
target/riscv: No need to re-start QEMU timer when timecmp ==
UINT64_MAX
target/riscv: Ensure opcode is saved for all relevant instructions
target/riscv/cpu_helper.c | 2 --
target/riscv/csr.c | 18 +++++++++++++++++-
target/riscv/insn_trans/trans_rva.c.inc | 10 +++++++---
target/riscv/insn_trans/trans_rvd.c.inc | 2 ++
target/riscv/insn_trans/trans_rvf.c.inc | 2 ++
target/riscv/insn_trans/trans_rvh.c.inc | 3 +++
target/riscv/insn_trans/trans_rvi.c.inc | 2 ++
target/riscv/insn_trans/trans_rvzfh.c.inc | 2 ++
target/riscv/insn_trans/trans_svinval.c.inc | 3 +++
target/riscv/time_helper.c | 20 ++++++++++++++++----
10 files changed, 54 insertions(+), 10 deletions(-)
--
2.34.1
next reply other threads:[~2022-10-27 16:50 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-27 16:47 Anup Patel [this message]
2022-10-27 16:47 ` [PATCH 1/5] target/riscv: Typo fix in sstc() predicate Anup Patel
2022-10-31 0:40 ` Alistair Francis
2022-10-27 16:47 ` [PATCH 2/5] target/riscv: Update VS timer whenever htimedelta changes Anup Patel
2022-10-31 0:42 ` Alistair Francis
2022-10-27 16:47 ` [PATCH 3/5] target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP Anup Patel
2022-10-31 0:44 ` Alistair Francis
2022-10-27 16:47 ` [PATCH 4/5] target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX Anup Patel
2022-10-31 0:55 ` Alistair Francis
2022-10-31 3:49 ` Anup Patel
2022-11-02 0:10 ` Alistair Francis
2022-11-07 2:48 ` Anup Patel
2022-10-27 16:47 ` [PATCH 5/5] target/riscv: Ensure opcode is saved for all relevant instructions Anup Patel
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