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([172.58.176.235]) by smtp.gmail.com with ESMTPSA id u8-20020a9d4d88000000b006618586b850sm2473857otk.46.2022.10.30.22.39.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 22:39:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 00/11] tcg patch queue Date: Mon, 31 Oct 2022 16:39:37 +1100 Message-Id: <20221031053948.3408-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::22d; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The following changes since commit 75d30fde55485b965a1168a21d016dd07b50ed32: Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2022-10-30 15:07:25 -0400) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20221031 for you to fetch changes up to cb375590983fc3d23600d02ba05a05d34fe44150: target/i386: Expand eflags updates inline (2022-10-31 11:39:10 +1100) ---------------------------------------------------------------- Remove sparc32plus support from tcg/sparc. target/i386: Use cpu_unwind_state_data for tpr access. target/i386: Expand eflags updates inline ---------------------------------------------------------------- Icenowy Zheng (1): tcg/tci: fix logic error when registering helpers via FFI Richard Henderson (10): tcg/sparc: Remove support for sparc32plus tcg/sparc64: Rename from tcg/sparc tcg/sparc64: Remove sparc32plus constraints accel/tcg: Introduce cpu_unwind_state_data target/i386: Use cpu_unwind_state_data for tpr access target/openrisc: Always exit after mtspr npc target/openrisc: Use cpu_unwind_state_data for mfspr accel/tcg: Remove will_exit argument from cpu_restore_state accel/tcg: Remove reset_icount argument from cpu_restore_state_from_tb target/i386: Expand eflags updates inline meson.build | 4 +- accel/tcg/internal.h | 4 +- include/exec/exec-all.h | 24 ++- target/i386/helper.h | 5 - tcg/{sparc => sparc64}/tcg-target-con-set.h | 16 +- tcg/{sparc => sparc64}/tcg-target-con-str.h | 3 - tcg/{sparc => sparc64}/tcg-target.h | 11 -- accel/tcg/cpu-exec-common.c | 2 +- accel/tcg/tb-maint.c | 4 +- accel/tcg/translate-all.c | 91 +++++---- target/alpha/helper.c | 2 +- target/alpha/mem_helper.c | 2 +- target/arm/op_helper.c | 2 +- target/arm/tlb_helper.c | 8 +- target/cris/helper.c | 2 +- target/i386/helper.c | 21 ++- target/i386/tcg/cc_helper.c | 41 ----- target/i386/tcg/sysemu/svm_helper.c | 2 +- target/i386/tcg/translate.c | 30 ++- target/m68k/op_helper.c | 4 +- target/microblaze/helper.c | 2 +- target/nios2/op_helper.c | 2 +- target/openrisc/sys_helper.c | 17 +- target/ppc/excp_helper.c | 2 +- target/s390x/tcg/excp_helper.c | 2 +- target/tricore/op_helper.c | 2 +- target/xtensa/helper.c | 6 +- tcg/tcg.c | 81 +------- tcg/{sparc => sparc64}/tcg-target.c.inc | 275 ++++++++-------------------- MAINTAINERS | 2 +- 30 files changed, 232 insertions(+), 437 deletions(-) rename tcg/{sparc => sparc64}/tcg-target-con-set.h (69%) rename tcg/{sparc => sparc64}/tcg-target-con-str.h (77%) rename tcg/{sparc => sparc64}/tcg-target.h (95%) rename tcg/{sparc => sparc64}/tcg-target.c.inc (91%)