[PATCH v5 0/6] ppc/e500: Add support for two types of flash, cleanup

[PATCH v5 0/6] ppc/e500: Add support for two types of flash, cleanup

[Philippe Mathieu-Daudé]

This is a respin of Bernhard's v4 with Freescale eSDHC implemented
as an 'UNIMP' region. See v4 cover here:
https://lore.kernel.org/qemu-devel/20221018210146.193159-1-shentey@gmail.com/

Only tested with the ppce500 machine (no further regression testing).

Since v4:
- Do not rename ESDHC_* definitions to USDHC_*
- Do not modify SDHCIState structure

Bernhard Beschow (4):
  hw/block/pflash_cfi0{1, 2}: Error out if device length isn't a power
    of two
  docs/system/ppc/ppce500: Use qemu-system-ppc64 across the board(s)
  hw/ppc/e500: Implement pflash handling
  hw/ppc/e500: Add Freescale eSDHC to e500plat

Philippe Mathieu-Daudé (2):
  hw/sd/sdhci: MMIO region is implemented in 32-bit accesses
  hw/sd/sdhci: Map host controller interface in host endianess

 docs/system/ppc/ppce500.rst |  38 +++++++++--
 hw/block/pflash_cfi01.c     |   8 ++-
 hw/block/pflash_cfi02.c     |   5 ++
 hw/ppc/Kconfig              |   3 +
 hw/ppc/e500.c               | 127 +++++++++++++++++++++++++++++++++++-
 hw/ppc/e500.h               |   1 +
 hw/ppc/e500plat.c           |   1 +
 hw/sd/sdhci.c               |   6 +-
 8 files changed, 180 insertions(+), 9 deletions(-)

-- 
2.37.3

[PATCH v5 1/6] hw/sd/sdhci: MMIO region is implemented in 32-bit accesses

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/sd/sdhci.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 0e5e988927..f9c5b58e6d 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -1332,6 +1332,10 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
 static const MemoryRegionOps sdhci_mmio_ops = {
     .read = sdhci_read,
     .write = sdhci_write,
+    .impl = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
     .valid = {
         .min_access_size = 1,
         .max_access_size = 4,
-- 
2.37.3

Re: [PATCH v5 1/6] hw/sd/sdhci: MMIO region is implemented in 32-bit accesses

[Bernhard Beschow]

Am 31. Oktober 2022 11:53:57 UTC schrieb "Philippe Mathieu-Daudé" <philmd@linaro.org>:
>Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Indeed there is `offset & ~0x3` in both sdhci_{read,write}, so:
Reviewed-by: Bernhard Beschow <shentey@gmail.com>

>---
> hw/sd/sdhci.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
>diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
>index 0e5e988927..f9c5b58e6d 100644
>--- a/hw/sd/sdhci.c
>+++ b/hw/sd/sdhci.c
>@@ -1332,6 +1332,10 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
> static const MemoryRegionOps sdhci_mmio_ops = {
>     .read = sdhci_read,
>     .write = sdhci_write,
>+    .impl = {
>+        .min_access_size = 4,
>+        .max_access_size = 4,
>+    },
>     .valid = {
>         .min_access_size = 1,
>         .max_access_size = 4,

[RFC PATCH v5 2/6] hw/sd/sdhci: Map host controller interface in host endianess

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/sd/sdhci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index f9c5b58e6d..40f37694d5 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -1341,7 +1341,7 @@ static const MemoryRegionOps sdhci_mmio_ops = {
         .max_access_size = 4,
         .unaligned = false
     },
-    .endianness = DEVICE_LITTLE_ENDIAN,
+    .endianness = DEVICE_NATIVE_ENDIAN,
 };
 
 static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp)
-- 
2.37.3

Re: [RFC PATCH v5 2/6] hw/sd/sdhci: Map host controller interface in host endianess

[Philippe Mathieu-Daudé]

On 31/10/22 12:53, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   hw/sd/sdhci.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
> index f9c5b58e6d..40f37694d5 100644
> --- a/hw/sd/sdhci.c
> +++ b/hw/sd/sdhci.c
> @@ -1341,7 +1341,7 @@ static const MemoryRegionOps sdhci_mmio_ops = {
>           .max_access_size = 4,
>           .unaligned = false
>       },
> -    .endianness = DEVICE_LITTLE_ENDIAN,
> +    .endianness = DEVICE_NATIVE_ENDIAN,
>   };

RFC because I was focusing on the SDHCI device and wanted some code
Bernhard could test. I expect something in the CCSR block doing the
endianness swapping.

[PATCH v5 3/6] hw/block/pflash_cfi0{1, 2}: Error out if device length isn't a power of two

[Philippe Mathieu-Daudé]

From: Bernhard Beschow <shentey@gmail.com>

According to the JEDEC standard the device length is communicated to an
OS as an exponent (power of two).

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20221018210146.193159-3-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/block/pflash_cfi01.c | 8 ++++++--
 hw/block/pflash_cfi02.c | 5 +++++
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c
index 0cbc2fb4cb..9c235bf66e 100644
--- a/hw/block/pflash_cfi01.c
+++ b/hw/block/pflash_cfi01.c
@@ -690,7 +690,7 @@ static const MemoryRegionOps pflash_cfi01_ops = {
     .endianness = DEVICE_NATIVE_ENDIAN,
 };
 
-static void pflash_cfi01_fill_cfi_table(PFlashCFI01 *pfl)
+static void pflash_cfi01_fill_cfi_table(PFlashCFI01 *pfl, Error **errp)
 {
     uint64_t blocks_per_device, sector_len_per_device, device_len;
     int num_devices;
@@ -708,6 +708,10 @@ static void pflash_cfi01_fill_cfi_table(PFlashCFI01 *pfl)
         sector_len_per_device = pfl->sector_len / num_devices;
     }
     device_len = sector_len_per_device * blocks_per_device;
+    if (!is_power_of_2(device_len)) {
+        error_setg(errp, "Device size must be a power of two.");
+        return;
+    }
 
     /* Hardcoded CFI table */
     /* Standard "QRY" string */
@@ -865,7 +869,7 @@ static void pflash_cfi01_realize(DeviceState *dev, Error **errp)
      */
     pfl->cmd = 0x00;
     pfl->status = 0x80; /* WSM ready */
-    pflash_cfi01_fill_cfi_table(pfl);
+    pflash_cfi01_fill_cfi_table(pfl, errp);
 }
 
 static void pflash_cfi01_system_reset(DeviceState *dev)
diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c
index 2a99b286b0..ff2fe154c1 100644
--- a/hw/block/pflash_cfi02.c
+++ b/hw/block/pflash_cfi02.c
@@ -880,6 +880,11 @@ static void pflash_cfi02_realize(DeviceState *dev, Error **errp)
         return;
     }
 
+    if (!is_power_of_2(pfl->chip_len)) {
+        error_setg(errp, "Device size must be a power of two.");
+        return;
+    }
+
     memory_region_init_rom_device(&pfl->orig_mem, OBJECT(pfl),
                                   &pflash_cfi02_ops, pfl, pfl->name,
                                   pfl->chip_len, errp);
-- 
2.37.3

[PATCH v5 4/6] docs/system/ppc/ppce500: Use qemu-system-ppc64 across the board(s)

[Philippe Mathieu-Daudé]

From: Bernhard Beschow <shentey@gmail.com>

The documentation suggests that there is a qemu-system-ppc32 binary
while the 32 bit version is actually just named qemu-system-ppc. Settle
on qemu-system-ppc64 which also works for 32 bit machines and causes
less clutter in the documentation.

Found-by: BALATON Zoltan <balaton@eik.bme.hu>
Suggested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20221018210146.193159-2-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 docs/system/ppc/ppce500.rst | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/docs/system/ppc/ppce500.rst b/docs/system/ppc/ppce500.rst
index ba6bcb7314..7b5eb3c4ee 100644
--- a/docs/system/ppc/ppce500.rst
+++ b/docs/system/ppc/ppce500.rst
@@ -113,7 +113,7 @@ To boot the 32-bit Linux kernel:
 
 .. code-block:: bash
 
-  $ qemu-system-ppc{64|32} -M ppce500 -cpu e500mc -smp 4 -m 2G \
+  $ qemu-system-ppc64 -M ppce500 -cpu e500mc -smp 4 -m 2G \
       -display none -serial stdio \
       -kernel vmlinux \
       -initrd /path/to/rootfs.cpio \
@@ -154,10 +154,10 @@ interface at PCI address 0.1.0, but we can switch that to an e1000 NIC by:
 
 .. code-block:: bash
 
-  $ qemu-system-ppc -M ppce500 -smp 4 -m 2G \
-                    -display none -serial stdio \
-                    -bios u-boot \
-                    -nic tap,ifname=tap0,script=no,downscript=no,model=e1000
+  $ qemu-system-ppc64 -M ppce500 -smp 4 -m 2G \
+                      -display none -serial stdio \
+                      -bios u-boot \
+                      -nic tap,ifname=tap0,script=no,downscript=no,model=e1000
 
 The QEMU ``ppce500`` machine can also dynamically instantiate an eTSEC device
 if “-device eTSEC” is given to QEMU:
-- 
2.37.3

[PATCH v5 5/6] hw/ppc/e500: Implement pflash handling

[Philippe Mathieu-Daudé]

From: Bernhard Beschow <shentey@gmail.com>

Allows e500 boards to have their root file system reside on flash using
only builtin devices located in the eLBC memory region.

Note that the flash memory area is only created when a -pflash argument is
given, and that the size is determined by the given file. The idea is to
put users into control.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221018210146.193159-6-shentey@gmail.com>
[PMD: Use memory_region_size()]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 docs/system/ppc/ppce500.rst | 16 ++++++++
 hw/ppc/Kconfig              |  1 +
 hw/ppc/e500.c               | 79 +++++++++++++++++++++++++++++++++++++
 3 files changed, 96 insertions(+)

diff --git a/docs/system/ppc/ppce500.rst b/docs/system/ppc/ppce500.rst
index 7b5eb3c4ee..38f8ceb0cf 100644
--- a/docs/system/ppc/ppce500.rst
+++ b/docs/system/ppc/ppce500.rst
@@ -165,3 +165,19 @@ if “-device eTSEC” is given to QEMU:
 .. code-block:: bash
 
   -netdev tap,ifname=tap0,script=no,downscript=no,id=net0 -device eTSEC,netdev=net0
+
+Root file system on flash drive
+-------------------------------
+
+Rather than using a root file system on ram disk, it is possible to have it on
+CFI flash. Given an ext2 image whose size must be a power of two, it can be used
+as follows:
+
+.. code-block:: bash
+
+  $ qemu-system-ppc64 -M ppce500 -cpu e500mc -smp 4 -m 2G \
+      -display none -serial stdio \
+      -kernel vmlinux \
+      -drive if=pflash,file=/path/to/rootfs.ext2,format=raw \
+      -append "rootwait root=/dev/mtdblock0"
+
diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
index 791fe78a50..769a1ead1c 100644
--- a/hw/ppc/Kconfig
+++ b/hw/ppc/Kconfig
@@ -126,6 +126,7 @@ config E500
     select ETSEC
     select GPIO_MPC8XXX
     select OPENPIC
+    select PFLASH_CFI01
     select PLATFORM_BUS
     select PPCE500_PCI
     select SERIAL
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index 3e950ea3ba..84bcc25526 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -23,8 +23,10 @@
 #include "e500-ccsr.h"
 #include "net/net.h"
 #include "qemu/config-file.h"
+#include "hw/block/flash.h"
 #include "hw/char/serial.h"
 #include "hw/pci/pci.h"
+#include "sysemu/block-backend-io.h"
 #include "sysemu/sysemu.h"
 #include "sysemu/kvm.h"
 #include "sysemu/reset.h"
@@ -267,6 +269,31 @@ static void sysbus_device_create_devtree(SysBusDevice *sbdev, void *opaque)
     }
 }
 
+static void create_devtree_flash(SysBusDevice *sbdev,
+                                 PlatformDevtreeData *data)
+{
+    g_autofree char *name = NULL;
+    uint64_t num_blocks = object_property_get_uint(OBJECT(sbdev),
+                                                   "num-blocks",
+                                                   &error_fatal);
+    uint64_t sector_length = object_property_get_uint(OBJECT(sbdev),
+                                                      "sector-length",
+                                                      &error_fatal);
+    uint64_t bank_width = object_property_get_uint(OBJECT(sbdev),
+                                                   "width",
+                                                   &error_fatal);
+    hwaddr flashbase = 0;
+    hwaddr flashsize = num_blocks * sector_length;
+    void *fdt = data->fdt;
+
+    name = g_strdup_printf("%s/nor@%" PRIx64, data->node, flashbase);
+    qemu_fdt_add_subnode(fdt, name);
+    qemu_fdt_setprop_string(fdt, name, "compatible", "cfi-flash");
+    qemu_fdt_setprop_sized_cells(fdt, name, "reg",
+                                 1, flashbase, 1, flashsize);
+    qemu_fdt_setprop_cell(fdt, name, "bank-width", bank_width);
+}
+
 static void platform_bus_create_devtree(PPCE500MachineState *pms,
                                         void *fdt, const char *mpic)
 {
@@ -276,6 +303,8 @@ static void platform_bus_create_devtree(PPCE500MachineState *pms,
     uint64_t addr = pmc->platform_bus_base;
     uint64_t size = pmc->platform_bus_size;
     int irq_start = pmc->platform_bus_first_irq;
+    SysBusDevice *sbdev;
+    bool ambiguous;
 
     /* Create a /platform node that we can put all devices into */
 
@@ -302,6 +331,13 @@ static void platform_bus_create_devtree(PPCE500MachineState *pms,
     /* Loop through all dynamic sysbus devices and create nodes for them */
     foreach_dynamic_sysbus_device(sysbus_device_create_devtree, &data);
 
+    sbdev = SYS_BUS_DEVICE(object_resolve_path_type("", TYPE_PFLASH_CFI01,
+                                                    &ambiguous));
+    if (sbdev) {
+        assert(!ambiguous);
+        create_devtree_flash(sbdev, &data);
+    }
+
     g_free(node);
 }
 
@@ -856,6 +892,7 @@ void ppce500_init(MachineState *machine)
     unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4};
     IrqLines *irqs;
     DeviceState *dev, *mpicdev;
+    DriveInfo *dinfo;
     CPUPPCState *firstenv = NULL;
     MemoryRegion *ccsr_addr_space;
     SysBusDevice *s;
@@ -1024,6 +1061,48 @@ void ppce500_init(MachineState *machine)
                                 pmc->platform_bus_base,
                                 &pms->pbus_dev->mmio);
 
+    dinfo = drive_get(IF_PFLASH, 0, 0);
+    if (dinfo) {
+        BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
+        BlockDriverState *bs = blk_bs(blk);
+        uint64_t size = bdrv_getlength(bs);
+        uint32_t sector_len = 64 * KiB;
+        uint64_t mmio_size = memory_region_size(&pms->pbus_dev->mmio);
+
+        if (!is_power_of_2(size)) {
+            error_report("Size of pflash file must be a power of two.");
+            exit(1);
+        }
+
+        if (size > mmio_size) {
+            error_report("Size of pflash file must not be bigger than %" PRIu64
+                         " bytes.", mmio_size);
+            exit(1);
+        }
+
+        if (!QEMU_IS_ALIGNED(size, sector_len)) {
+            error_report("Size of pflash file must be a multiple of %" PRIu32
+                         ".", sector_len);
+            exit(1);
+        }
+
+        dev = qdev_new(TYPE_PFLASH_CFI01);
+        qdev_prop_set_drive(dev, "drive", blk);
+        qdev_prop_set_uint32(dev, "num-blocks", size / sector_len);
+        qdev_prop_set_uint64(dev, "sector-length", sector_len);
+        qdev_prop_set_uint8(dev, "width", 2);
+        qdev_prop_set_bit(dev, "big-endian", true);
+        qdev_prop_set_uint16(dev, "id0", 0x89);
+        qdev_prop_set_uint16(dev, "id1", 0x18);
+        qdev_prop_set_uint16(dev, "id2", 0x0000);
+        qdev_prop_set_uint16(dev, "id3", 0x0);
+        qdev_prop_set_string(dev, "name", "e500.flash");
+        sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+
+        memory_region_add_subregion(&pms->pbus_dev->mmio, 0,
+                                    pflash_cfi01_get_memory(PFLASH_CFI01(dev)));
+    }
+
     /*
      * Smart firmware defaults ahead!
      *
-- 
2.37.3

[PATCH v5 6/6] hw/ppc/e500: Add Freescale eSDHC to e500plat

[Philippe Mathieu-Daudé]

From: Bernhard Beschow <shentey@gmail.com>

Adds missing functionality to e500plat machine which increases the
chance of given "real" firmware images to access SD cards.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20221018210146.193159-8-shentey@gmail.com>
[PMD: Simplify using create_unimplemented_device("esdhc")]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 docs/system/ppc/ppce500.rst | 12 ++++++++++
 hw/ppc/Kconfig              |  2 ++
 hw/ppc/e500.c               | 48 ++++++++++++++++++++++++++++++++++++-
 hw/ppc/e500.h               |  1 +
 hw/ppc/e500plat.c           |  1 +
 5 files changed, 63 insertions(+), 1 deletion(-)

diff --git a/docs/system/ppc/ppce500.rst b/docs/system/ppc/ppce500.rst
index 38f8ceb0cf..c9fe0915dc 100644
--- a/docs/system/ppc/ppce500.rst
+++ b/docs/system/ppc/ppce500.rst
@@ -19,6 +19,7 @@ The ``ppce500`` machine supports the following devices:
 * Power-off functionality via one GPIO pin
 * 1 Freescale MPC8xxx PCI host controller
 * VirtIO devices via PCI bus
+* 1 Freescale Enhanced Secure Digital Host controller (eSDHC)
 * 1 Freescale Enhanced Triple Speed Ethernet controller (eTSEC)
 
 Hardware configuration information
@@ -181,3 +182,14 @@ as follows:
       -drive if=pflash,file=/path/to/rootfs.ext2,format=raw \
       -append "rootwait root=/dev/mtdblock0"
 
+Alternatively, the root file system can also reside on an emulated SD card
+whose size must again be a power of two:
+
+.. code-block:: bash
+
+  $ qemu-system-ppc64 -M ppce500 -cpu e500mc -smp 4 -m 2G \
+      -display none -serial stdio \
+      -kernel vmlinux \
+      -device sd-card,drive=mydrive \
+      -drive id=mydrive,if=none,file=/path/to/rootfs.ext2,format=raw \
+      -append "rootwait root=/dev/mmcblk0"
diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
index 769a1ead1c..c48aaaa9dc 100644
--- a/hw/ppc/Kconfig
+++ b/hw/ppc/Kconfig
@@ -129,10 +129,12 @@ config E500
     select PFLASH_CFI01
     select PLATFORM_BUS
     select PPCE500_PCI
+    select SDHCI
     select SERIAL
     select MPC_I2C
     select FDT_PPC
     select DS1338
+    select UNIMP
 
 config E500PLAT
     bool
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index 84bcc25526..80e4c4c4ca 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -48,6 +48,8 @@
 #include "hw/net/fsl_etsec/etsec.h"
 #include "hw/i2c/i2c.h"
 #include "hw/irq.h"
+#include "hw/sd/sdhci.h"
+#include "hw/misc/unimp.h"
 
 #define EPAPR_MAGIC                (0x45504150)
 #define DTC_LOAD_PAD               0x1800000
@@ -66,11 +68,14 @@
 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
 #define MPC8544_PCI_REGS_OFFSET    0x8000ULL
 #define MPC8544_PCI_REGS_SIZE      0x1000ULL
+#define MPC85XX_ESDHC_REGS_OFFSET  0x2e000ULL
+#define MPC85XX_ESDHC_REGS_SIZE    0x1000ULL
 #define MPC8544_UTIL_OFFSET        0xe0000ULL
 #define MPC8XXX_GPIO_OFFSET        0x000FF000ULL
 #define MPC8544_I2C_REGS_OFFSET    0x3000ULL
 #define MPC8XXX_GPIO_IRQ           47
 #define MPC8544_I2C_IRQ            43
+#define MPC85XX_ESDHC_IRQ          72
 #define RTC_REGS_OFFSET            0x68
 
 #define PLATFORM_CLK_FREQ_HZ       (400 * 1000 * 1000)
@@ -203,6 +208,22 @@ static void dt_i2c_create(void *fdt, const char *soc, const char *mpic,
     g_free(i2c);
 }
 
+static void dt_sdhc_create(void *fdt, const char *parent, const char *mpic)
+{
+    hwaddr mmio = MPC85XX_ESDHC_REGS_OFFSET;
+    hwaddr size = MPC85XX_ESDHC_REGS_SIZE;
+    int irq = MPC85XX_ESDHC_IRQ;
+    g_autofree char *name = NULL;
+
+    name = g_strdup_printf("%s/sdhc@%" PRIx64, parent, mmio);
+    qemu_fdt_add_subnode(fdt, name);
+    qemu_fdt_setprop(fdt, name, "sdhci,auto-cmd12", NULL, 0);
+    qemu_fdt_setprop_phandle(fdt, name, "interrupt-parent", mpic);
+    qemu_fdt_setprop_cells(fdt, name, "bus-width", 4);
+    qemu_fdt_setprop_cells(fdt, name, "interrupts", irq, 0x2);
+    qemu_fdt_setprop_cells(fdt, name, "reg", mmio, size);
+    qemu_fdt_setprop_string(fdt, name, "compatible", "fsl,esdhc");
+}
 
 typedef struct PlatformDevtreeData {
     void *fdt;
@@ -553,6 +574,10 @@ static int ppce500_load_device_tree(PPCE500MachineState *pms,
 
     dt_rtc_create(fdt, "i2c", "rtc");
 
+    /* sdhc */
+    if (pmc->has_esdhc) {
+        dt_sdhc_create(fdt, soc, mpic);
+    }
 
     gutil = g_strdup_printf("%s/global-utilities@%llx", soc,
                             MPC8544_UTIL_OFFSET);
@@ -982,7 +1007,8 @@ void ppce500_init(MachineState *machine)
                        0, qdev_get_gpio_in(mpicdev, 42), 399193,
                        serial_hd(1), DEVICE_BIG_ENDIAN);
     }
-        /* I2C */
+
+    /* I2C */
     dev = qdev_new("mpc-i2c");
     s = SYS_BUS_DEVICE(dev);
     sysbus_realize_and_unref(s, &error_fatal);
@@ -992,6 +1018,26 @@ void ppce500_init(MachineState *machine)
     i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
     i2c_slave_create_simple(i2c, "ds1338", RTC_REGS_OFFSET);
 
+    /* eSDHC */
+    if (pmc->has_esdhc) {
+        uint64_t sdhci_regsize;
+
+        dev = qdev_new(TYPE_SYSBUS_SDHCI);
+        /*
+         * Compatible with:
+         * - SD Host Controller Specification Version 2.0 Part A2
+         */
+        qdev_prop_set_uint8(dev, "sd-spec-version", 2);
+        s = SYS_BUS_DEVICE(dev);
+        sysbus_realize_and_unref(s, &error_fatal);
+        sysbus_mmio_map(s, 0, pmc->ccsrbar_base + MPC85XX_ESDHC_REGS_OFFSET);
+        sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC85XX_ESDHC_IRQ));
+        sdhci_regsize = memory_region_size(sysbus_mmio_get_region(s, 0));
+        create_unimplemented_device("esdhc",
+                                    pmc->ccsrbar_base
+                                    + MPC85XX_ESDHC_REGS_OFFSET + sdhci_regsize,
+                                    MPC85XX_ESDHC_REGS_SIZE - sdhci_regsize);
+    }
 
     /* General Utility device */
     dev = qdev_new("mpc8544-guts");
diff --git a/hw/ppc/e500.h b/hw/ppc/e500.h
index 68f754ce50..8c09ef92e4 100644
--- a/hw/ppc/e500.h
+++ b/hw/ppc/e500.h
@@ -27,6 +27,7 @@ struct PPCE500MachineClass {
 
     int mpic_version;
     bool has_mpc8xxx_gpio;
+    bool has_esdhc;
     hwaddr platform_bus_base;
     hwaddr platform_bus_size;
     int platform_bus_first_irq;
diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c
index 5bb1c603da..44bf874b0f 100644
--- a/hw/ppc/e500plat.c
+++ b/hw/ppc/e500plat.c
@@ -86,6 +86,7 @@ static void e500plat_machine_class_init(ObjectClass *oc, void *data)
     pmc->fixup_devtree = e500plat_fixup_devtree;
     pmc->mpic_version = OPENPIC_MODEL_FSL_MPIC_42;
     pmc->has_mpc8xxx_gpio = true;
+    pmc->has_esdhc = true;
     pmc->platform_bus_base = 0xf00000000ULL;
     pmc->platform_bus_size = 128 * MiB;
     pmc->platform_bus_first_irq = 5;
-- 
2.37.3

Re: [PATCH v5 6/6] hw/ppc/e500: Add Freescale eSDHC to e500plat

[Philippe Mathieu-Daudé]

On 31/10/22 12:54, Philippe Mathieu-Daudé wrote:
> From: Bernhard Beschow <shentey@gmail.com>
> 
> Adds missing functionality to e500plat machine which increases the
> chance of given "real" firmware images to access SD cards.
> 
> Signed-off-by: Bernhard Beschow <shentey@gmail.com>
> Message-Id: <20221018210146.193159-8-shentey@gmail.com>
> [PMD: Simplify using create_unimplemented_device("esdhc")]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   docs/system/ppc/ppce500.rst | 12 ++++++++++
>   hw/ppc/Kconfig              |  2 ++
>   hw/ppc/e500.c               | 48 ++++++++++++++++++++++++++++++++++++-
>   hw/ppc/e500.h               |  1 +
>   hw/ppc/e500plat.c           |  1 +
>   5 files changed, 63 insertions(+), 1 deletion(-)

> @@ -992,6 +1018,26 @@ void ppce500_init(MachineState *machine)
>       i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
>       i2c_slave_create_simple(i2c, "ds1338", RTC_REGS_OFFSET);
>   
> +    /* eSDHC */
> +    if (pmc->has_esdhc) {
> +        uint64_t sdhci_regsize;
> +
> +        dev = qdev_new(TYPE_SYSBUS_SDHCI);
> +        /*
> +         * Compatible with:
> +         * - SD Host Controller Specification Version 2.0 Part A2
> +         */
> +        qdev_prop_set_uint8(dev, "sd-spec-version", 2);
> +        s = SYS_BUS_DEVICE(dev);
> +        sysbus_realize_and_unref(s, &error_fatal);
> +        sysbus_mmio_map(s, 0, pmc->ccsrbar_base + MPC85XX_ESDHC_REGS_OFFSET);
> +        sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC85XX_ESDHC_IRQ));
> +        sdhci_regsize = memory_region_size(sysbus_mmio_get_region(s, 0));
> +        create_unimplemented_device("esdhc",
> +                                    pmc->ccsrbar_base
> +                                    + MPC85XX_ESDHC_REGS_OFFSET + sdhci_regsize,
> +                                    MPC85XX_ESDHC_REGS_SIZE - sdhci_regsize);
> +    }

Since the UNIMP device has lower priority, we can simplify as:

if (pmc->has_esdhc) {
     create_unimplemented_device("esdhc",
                                 pmc->ccsrbar_base
                                 + MPC85XX_ESDHC_REGS_OFFSET,
                                 MPC85XX_ESDHC_REGS_SIZE);

     dev = qdev_new(TYPE_SYSBUS_SDHCI);
     /*
      * Compatible with:
      * - SD Host Controller Specification Version 2.0 Part A2
      */
     qdev_prop_set_uint8(dev, "sd-spec-version", 2);
     s = SYS_BUS_DEVICE(dev);
     sysbus_realize_and_unref(s, &error_fatal);
     sysbus_mmio_map(s, 0, pmc->ccsrbar_base + MPC85XX_ESDHC_REGS_OFFSET);
     sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC85XX_ESDHC_IRQ));
}

Re: [PATCH v5 6/6] hw/ppc/e500: Add Freescale eSDHC to e500plat

[Philippe Mathieu-Daudé]

On 31/10/22 16:12, Philippe Mathieu-Daudé wrote:
> On 31/10/22 12:54, Philippe Mathieu-Daudé wrote:
>> From: Bernhard Beschow <shentey@gmail.com>
>>
>> Adds missing functionality to e500plat machine which increases the
>> chance of given "real" firmware images to access SD cards.
>>
>> Signed-off-by: Bernhard Beschow <shentey@gmail.com>
>> Message-Id: <20221018210146.193159-8-shentey@gmail.com>
>> [PMD: Simplify using create_unimplemented_device("esdhc")]
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>>   docs/system/ppc/ppce500.rst | 12 ++++++++++
>>   hw/ppc/Kconfig              |  2 ++
>>   hw/ppc/e500.c               | 48 ++++++++++++++++++++++++++++++++++++-
>>   hw/ppc/e500.h               |  1 +
>>   hw/ppc/e500plat.c           |  1 +
>>   5 files changed, 63 insertions(+), 1 deletion(-)
> 
>> @@ -992,6 +1018,26 @@ void ppce500_init(MachineState *machine)
>>       i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
>>       i2c_slave_create_simple(i2c, "ds1338", RTC_REGS_OFFSET);
>> +    /* eSDHC */
>> +    if (pmc->has_esdhc) {
>> +        uint64_t sdhci_regsize;
>> +
>> +        dev = qdev_new(TYPE_SYSBUS_SDHCI);
>> +        /*
>> +         * Compatible with:
>> +         * - SD Host Controller Specification Version 2.0 Part A2
>> +         */
>> +        qdev_prop_set_uint8(dev, "sd-spec-version", 2);
>> +        s = SYS_BUS_DEVICE(dev);
>> +        sysbus_realize_and_unref(s, &error_fatal);
>> +        sysbus_mmio_map(s, 0, pmc->ccsrbar_base + 
>> MPC85XX_ESDHC_REGS_OFFSET);
>> +        sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, 
>> MPC85XX_ESDHC_IRQ));
>> +        sdhci_regsize = memory_region_size(sysbus_mmio_get_region(s, 
>> 0));
>> +        create_unimplemented_device("esdhc",
>> +                                    pmc->ccsrbar_base
>> +                                    + MPC85XX_ESDHC_REGS_OFFSET + 
>> sdhci_regsize,
>> +                                    MPC85XX_ESDHC_REGS_SIZE - 
>> sdhci_regsize);
>> +    }
> 
> Since the UNIMP device has lower priority, we can simplify as:
> 
> if (pmc->has_esdhc) {
>      create_unimplemented_device("esdhc",
>                                  pmc->ccsrbar_base
>                                  + MPC85XX_ESDHC_REGS_OFFSET,
>                                  MPC85XX_ESDHC_REGS_SIZE);
> 
>      dev = qdev_new(TYPE_SYSBUS_SDHCI);
>      /*
>       * Compatible with:
>       * - SD Host Controller Specification Version 2.0 Part A2
>       */
>      qdev_prop_set_uint8(dev, "sd-spec-version", 2);
>      s = SYS_BUS_DEVICE(dev);
>      sysbus_realize_and_unref(s, &error_fatal);
>      sysbus_mmio_map(s, 0, pmc->ccsrbar_base + MPC85XX_ESDHC_REGS_OFFSET);

So the SDHCI is mapped inside the CCSR block. Better would be to map it 
into ccsr_addr_space.

I presume the CCSR is the device responsible of endian swapping, but TBH
I have no clue about this board.

Re: [PATCH v5 6/6] hw/ppc/e500: Add Freescale eSDHC to e500plat

[Bernhard Beschow]

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On Mon, Oct 31, 2022 at 4:19 PM Philippe Mathieu-Daudé <philmd@linaro.org>
wrote:

> On 31/10/22 16:12, Philippe Mathieu-Daudé wrote:
> > On 31/10/22 12:54, Philippe Mathieu-Daudé wrote:
> >> From: Bernhard Beschow <shentey@gmail.com>
> >>
> >> Adds missing functionality to e500plat machine which increases the
> >> chance of given "real" firmware images to access SD cards.
> >>
> >> Signed-off-by: Bernhard Beschow <shentey@gmail.com>
> >> Message-Id: <20221018210146.193159-8-shentey@gmail.com>
> >> [PMD: Simplify using create_unimplemented_device("esdhc")]
> >> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> >> ---
> >>   docs/system/ppc/ppce500.rst | 12 ++++++++++
> >>   hw/ppc/Kconfig              |  2 ++
> >>   hw/ppc/e500.c               | 48 ++++++++++++++++++++++++++++++++++++-
> >>   hw/ppc/e500.h               |  1 +
> >>   hw/ppc/e500plat.c           |  1 +
> >>   5 files changed, 63 insertions(+), 1 deletion(-)
> >
> >> @@ -992,6 +1018,26 @@ void ppce500_init(MachineState *machine)
> >>       i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
> >>       i2c_slave_create_simple(i2c, "ds1338", RTC_REGS_OFFSET);
> >> +    /* eSDHC */
> >> +    if (pmc->has_esdhc) {
> >> +        uint64_t sdhci_regsize;
> >> +
> >> +        dev = qdev_new(TYPE_SYSBUS_SDHCI);
> >> +        /*
> >> +         * Compatible with:
> >> +         * - SD Host Controller Specification Version 2.0 Part A2
> >> +         */
> >> +        qdev_prop_set_uint8(dev, "sd-spec-version", 2);
> >> +        s = SYS_BUS_DEVICE(dev);
> >> +        sysbus_realize_and_unref(s, &error_fatal);
> >> +        sysbus_mmio_map(s, 0, pmc->ccsrbar_base +
> >> MPC85XX_ESDHC_REGS_OFFSET);
> >> +        sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev,
> >> MPC85XX_ESDHC_IRQ));
> >> +        sdhci_regsize = memory_region_size(sysbus_mmio_get_region(s,
> >> 0));
> >> +        create_unimplemented_device("esdhc",
> >> +                                    pmc->ccsrbar_base
> >> +                                    + MPC85XX_ESDHC_REGS_OFFSET +
> >> sdhci_regsize,
> >> +                                    MPC85XX_ESDHC_REGS_SIZE -
> >> sdhci_regsize);
> >> +    }
> >
> > Since the UNIMP device has lower priority, we can simplify as:
> >
> > if (pmc->has_esdhc) {
> >      create_unimplemented_device("esdhc",
> >                                  pmc->ccsrbar_base
> >                                  + MPC85XX_ESDHC_REGS_OFFSET,
> >                                  MPC85XX_ESDHC_REGS_SIZE);
> >
> >      dev = qdev_new(TYPE_SYSBUS_SDHCI);
> >      /*
> >       * Compatible with:
> >       * - SD Host Controller Specification Version 2.0 Part A2
> >       */
> >      qdev_prop_set_uint8(dev, "sd-spec-version", 2);
> >      s = SYS_BUS_DEVICE(dev);
> >      sysbus_realize_and_unref(s, &error_fatal);
> >      sysbus_mmio_map(s, 0, pmc->ccsrbar_base +
> MPC85XX_ESDHC_REGS_OFFSET);
>
  memory_region_add_subregion(ccsr_addr_space, MPC85XX_ESDHC_REGS_OFFSET,
                              sysbus_mmio_get_region(s, 0));

seems to be equivalent, works as well and mimics other devices, e.g. i2c.
So perhaps use that?

>
> So the SDHCI is mapped inside the CCSR block. Better would be to map it
> into ccsr_addr_space.
>

Doesn't the above code map it into ccsr_addr_space?

>
> I presume the CCSR is the device responsible of endian swapping, but TBH
> I have no clue about this board.
>
>

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Re: [PATCH v5 0/6] ppc/e500: Add support for two types of flash, cleanup

[Bernhard Beschow]

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On Mon, Oct 31, 2022 at 12:54 PM Philippe Mathieu-Daudé <philmd@linaro.org>
wrote:

> This is a respin of Bernhard's v4 with Freescale eSDHC implemented
> as an 'UNIMP' region. See v4 cover here:
>
> https://lore.kernel.org/qemu-devel/20221018210146.193159-1-shentey@gmail.com/
>
> Only tested with the ppce500 machine (no further regression testing).
>
> Since v4:
> - Do not rename ESDHC_* definitions to USDHC_*
> - Do not modify SDHCIState structure
>

Works beautifully, both for the buildroot load and for my proprietary load.
So:
Tested-by: Bernhard Beschow<shentey@gmail.com>

>
> Bernhard Beschow (4):
>   hw/block/pflash_cfi0{1, 2}: Error out if device length isn't a power
>     of two
>   docs/system/ppc/ppce500: Use qemu-system-ppc64 across the board(s)
>   hw/ppc/e500: Implement pflash handling
>   hw/ppc/e500: Add Freescale eSDHC to e500plat
>
> Philippe Mathieu-Daudé (2):
>   hw/sd/sdhci: MMIO region is implemented in 32-bit accesses
>   hw/sd/sdhci: Map host controller interface in host endianess
>
>  docs/system/ppc/ppce500.rst |  38 +++++++++--
>  hw/block/pflash_cfi01.c     |   8 ++-
>  hw/block/pflash_cfi02.c     |   5 ++
>  hw/ppc/Kconfig              |   3 +
>  hw/ppc/e500.c               | 127 +++++++++++++++++++++++++++++++++++-
>  hw/ppc/e500.h               |   1 +
>  hw/ppc/e500plat.c           |   1 +
>  hw/sd/sdhci.c               |   6 +-
>  8 files changed, 180 insertions(+), 9 deletions(-)
>
> --
> 2.37.3
>
>

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Re: [PATCH v5 0/6] ppc/e500: Add support for two types of flash, cleanup

[Bernhard Beschow]

Am 1. November 2022 10:41:51 UTC schrieb Bernhard Beschow <shentey@gmail.com>:
>On Mon, Oct 31, 2022 at 12:54 PM Philippe Mathieu-Daudé <philmd@linaro.org>
>wrote:
>
>> This is a respin of Bernhard's v4 with Freescale eSDHC implemented
>> as an 'UNIMP' region. See v4 cover here:
>>
>> https://lore.kernel.org/qemu-devel/20221018210146.193159-1-shentey@gmail.com/
>>
>> Only tested with the ppce500 machine (no further regression testing).
>>
>> Since v4:
>> - Do not rename ESDHC_* definitions to USDHC_*
>> - Do not modify SDHCIState structure
>>
>
>Works beautifully, both for the buildroot load and for my proprietary load.
>So:
>Tested-by: Bernhard Beschow<shentey@gmail.com>
>
>>
>> Bernhard Beschow (4):
>>   hw/block/pflash_cfi0{1, 2}: Error out if device length isn't a power
>>     of two
>>   docs/system/ppc/ppce500: Use qemu-system-ppc64 across the board(s)
>>   hw/ppc/e500: Implement pflash handling
>>   hw/ppc/e500: Add Freescale eSDHC to e500plat
>>
>> Philippe Mathieu-Daudé (2):
>>   hw/sd/sdhci: MMIO region is implemented in 32-bit accesses
>>   hw/sd/sdhci: Map host controller interface in host endianess

Hi Phil,

Is there a chance to get this in for 7.2?

Best regards,
Bernhard
>>
>>  docs/system/ppc/ppce500.rst |  38 +++++++++--
>>  hw/block/pflash_cfi01.c     |   8 ++-
>>  hw/block/pflash_cfi02.c     |   5 ++
>>  hw/ppc/Kconfig              |   3 +
>>  hw/ppc/e500.c               | 127 +++++++++++++++++++++++++++++++++++-
>>  hw/ppc/e500.h               |   1 +
>>  hw/ppc/e500plat.c           |   1 +
>>  hw/sd/sdhci.c               |   6 +-
>>  8 files changed, 180 insertions(+), 9 deletions(-)
>>
>> --
>> 2.37.3
>>
>>

Re: [PATCH v5 0/6] ppc/e500: Add support for two types of flash, cleanup

[Philippe Mathieu-Daudé]

On 1/11/22 17:01, Bernhard Beschow wrote:
> Am 1. November 2022 10:41:51 UTC schrieb Bernhard Beschow <shentey@gmail.com>:
>> On Mon, Oct 31, 2022 at 12:54 PM Philippe Mathieu-Daudé <philmd@linaro.org>
>> wrote:
>>
>>> This is a respin of Bernhard's v4 with Freescale eSDHC implemented
>>> as an 'UNIMP' region. See v4 cover here:
>>>
>>> https://lore.kernel.org/qemu-devel/20221018210146.193159-1-shentey@gmail.com/
>>>
>>> Only tested with the ppce500 machine (no further regression testing).
>>>
>>> Since v4:
>>> - Do not rename ESDHC_* definitions to USDHC_*
>>> - Do not modify SDHCIState structure
>>>
>>
>> Works beautifully, both for the buildroot load and for my proprietary load.
>> So:
>> Tested-by: Bernhard Beschow<shentey@gmail.com>
>>
>>>
>>> Bernhard Beschow (4):
>>>    hw/block/pflash_cfi0{1, 2}: Error out if device length isn't a power
>>>      of two
>>>    docs/system/ppc/ppce500: Use qemu-system-ppc64 across the board(s)
>>>    hw/ppc/e500: Implement pflash handling
>>>    hw/ppc/e500: Add Freescale eSDHC to e500plat
>>>
>>> Philippe Mathieu-Daudé (2):
>>>    hw/sd/sdhci: MMIO region is implemented in 32-bit accesses
>>>    hw/sd/sdhci: Map host controller interface in host endianess
> 
> Hi Phil,
> 
> Is there a chance to get this in for 7.2?

Well 1/ can you review patch #1 and 2/ we need to figure out what to do 
with patch #2 :) Can you point me to the CCSR datasheet?

Re: [PATCH v5 0/6] ppc/e500: Add support for two types of flash, cleanup

[Philippe Mathieu-Daudé]

On 1/11/22 17:58, Philippe Mathieu-Daudé wrote:
> On 1/11/22 17:01, Bernhard Beschow wrote:
>> Am 1. November 2022 10:41:51 UTC schrieb Bernhard Beschow 
>> <shentey@gmail.com>:
>>> On Mon, Oct 31, 2022 at 12:54 PM Philippe Mathieu-Daudé 
>>> <philmd@linaro.org>
>>> wrote:
>>>
>>>> This is a respin of Bernhard's v4 with Freescale eSDHC implemented
>>>> as an 'UNIMP' region. See v4 cover here:
>>>>
>>>> https://lore.kernel.org/qemu-devel/20221018210146.193159-1-shentey@gmail.com/

>> Hi Phil,
>>
>> Is there a chance to get this in for 7.2?
> 
> Well 1/ can you review patch #1 and 2/ we need to figure out what to do 
> with patch #2 :) Can you point me to the CCSR datasheet?

Maybe I found it, I'm looking at the "MPC8544E PowerQUICC III Integrated 
Host Processor Family Reference Manual, Rev. 1".

Re: [PATCH v5 0/6] ppc/e500: Add support for two types of flash, cleanup

[Philippe Mathieu-Daudé]

On 1/11/22 18:43, Philippe Mathieu-Daudé wrote:
> On 1/11/22 17:58, Philippe Mathieu-Daudé wrote:
>> On 1/11/22 17:01, Bernhard Beschow wrote:
>>> Am 1. November 2022 10:41:51 UTC schrieb Bernhard Beschow 
>>> <shentey@gmail.com>:
>>>> On Mon, Oct 31, 2022 at 12:54 PM Philippe Mathieu-Daudé 
>>>> <philmd@linaro.org>
>>>> wrote:
>>>>
>>>>> This is a respin of Bernhard's v4 with Freescale eSDHC implemented
>>>>> as an 'UNIMP' region. See v4 cover here:
>>>>>
>>>>> https://lore.kernel.org/qemu-devel/20221018210146.193159-1-shentey@gmail.com/
> 
>>> Hi Phil,
>>>
>>> Is there a chance to get this in for 7.2?
>>
>> Well 1/ can you review patch #1 and 2/ we need to figure out what to 
>> do with patch #2 :) Can you point me to the CCSR datasheet?
> 
> Maybe I found it, I'm looking at the "MPC8544E PowerQUICC III Integrated 
> Host Processor Family Reference Manual, Rev. 1".

On "Table 2-11. CCSR Block Base Address Map" I see the 0x2_7000–0x3_0FFF 
region marked as 'Reserved'. How does the eSDHC end mapped there?

Re: [PATCH v5 0/6] ppc/e500: Add support for two types of flash, cleanup

[B]

Am 1. November 2022 17:43:46 UTC schrieb "Philippe Mathieu-Daudé" <philmd@linaro.org>:
>On 1/11/22 17:58, Philippe Mathieu-Daudé wrote:
>> On 1/11/22 17:01, Bernhard Beschow wrote:
>>> Am 1. November 2022 10:41:51 UTC schrieb Bernhard Beschow <shentey@gmail.com>:
>>>> On Mon, Oct 31, 2022 at 12:54 PM Philippe Mathieu-Daudé <philmd@linaro.org>
>>>> wrote:
>>>> 
>>>>> This is a respin of Bernhard's v4 with Freescale eSDHC implemented
>>>>> as an 'UNIMP' region. See v4 cover here:
>>>>> 
>>>>> https://lore.kernel.org/qemu-devel/20221018210146.193159-1-shentey@gmail.com/
>
>>> Hi Phil,
>>> 
>>> Is there a chance to get this in for 7.2?
>> 
>> Well 1/ can you review patch #1 and 2/ we need to figure out what to do with patch #2 :) Can you point me to the CCSR datasheet?
>
>Maybe I found it, I'm looking at the "MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1".

This document looks similar to mine: https://www.nxp.com/docs/en/reference-manual/MPC8569ERM.pdf

Best regards,
Bernhard