From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org, Bernhard Beschow <shentey@gmail.com>
Cc: "Daniel Henrique Barboza" <danielhb413@gmail.com>,
"Hanna Reitz" <hreitz@redhat.com>,
qemu-ppc@nongnu.org, "Bin Meng" <bin.meng@windriver.com>,
"Kevin Wolf" <kwolf@redhat.com>,
qemu-block@nongnu.org,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH v5 6/6] hw/ppc/e500: Add Freescale eSDHC to e500plat
Date: Mon, 31 Oct 2022 12:54:02 +0100 [thread overview]
Message-ID: <20221031115402.91912-7-philmd@linaro.org> (raw)
In-Reply-To: <20221031115402.91912-1-philmd@linaro.org>
From: Bernhard Beschow <shentey@gmail.com>
Adds missing functionality to e500plat machine which increases the
chance of given "real" firmware images to access SD cards.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20221018210146.193159-8-shentey@gmail.com>
[PMD: Simplify using create_unimplemented_device("esdhc")]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
docs/system/ppc/ppce500.rst | 12 ++++++++++
hw/ppc/Kconfig | 2 ++
hw/ppc/e500.c | 48 ++++++++++++++++++++++++++++++++++++-
hw/ppc/e500.h | 1 +
hw/ppc/e500plat.c | 1 +
5 files changed, 63 insertions(+), 1 deletion(-)
diff --git a/docs/system/ppc/ppce500.rst b/docs/system/ppc/ppce500.rst
index 38f8ceb0cf..c9fe0915dc 100644
--- a/docs/system/ppc/ppce500.rst
+++ b/docs/system/ppc/ppce500.rst
@@ -19,6 +19,7 @@ The ``ppce500`` machine supports the following devices:
* Power-off functionality via one GPIO pin
* 1 Freescale MPC8xxx PCI host controller
* VirtIO devices via PCI bus
+* 1 Freescale Enhanced Secure Digital Host controller (eSDHC)
* 1 Freescale Enhanced Triple Speed Ethernet controller (eTSEC)
Hardware configuration information
@@ -181,3 +182,14 @@ as follows:
-drive if=pflash,file=/path/to/rootfs.ext2,format=raw \
-append "rootwait root=/dev/mtdblock0"
+Alternatively, the root file system can also reside on an emulated SD card
+whose size must again be a power of two:
+
+.. code-block:: bash
+
+ $ qemu-system-ppc64 -M ppce500 -cpu e500mc -smp 4 -m 2G \
+ -display none -serial stdio \
+ -kernel vmlinux \
+ -device sd-card,drive=mydrive \
+ -drive id=mydrive,if=none,file=/path/to/rootfs.ext2,format=raw \
+ -append "rootwait root=/dev/mmcblk0"
diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
index 769a1ead1c..c48aaaa9dc 100644
--- a/hw/ppc/Kconfig
+++ b/hw/ppc/Kconfig
@@ -129,10 +129,12 @@ config E500
select PFLASH_CFI01
select PLATFORM_BUS
select PPCE500_PCI
+ select SDHCI
select SERIAL
select MPC_I2C
select FDT_PPC
select DS1338
+ select UNIMP
config E500PLAT
bool
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index 84bcc25526..80e4c4c4ca 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -48,6 +48,8 @@
#include "hw/net/fsl_etsec/etsec.h"
#include "hw/i2c/i2c.h"
#include "hw/irq.h"
+#include "hw/sd/sdhci.h"
+#include "hw/misc/unimp.h"
#define EPAPR_MAGIC (0x45504150)
#define DTC_LOAD_PAD 0x1800000
@@ -66,11 +68,14 @@
#define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
#define MPC8544_PCI_REGS_OFFSET 0x8000ULL
#define MPC8544_PCI_REGS_SIZE 0x1000ULL
+#define MPC85XX_ESDHC_REGS_OFFSET 0x2e000ULL
+#define MPC85XX_ESDHC_REGS_SIZE 0x1000ULL
#define MPC8544_UTIL_OFFSET 0xe0000ULL
#define MPC8XXX_GPIO_OFFSET 0x000FF000ULL
#define MPC8544_I2C_REGS_OFFSET 0x3000ULL
#define MPC8XXX_GPIO_IRQ 47
#define MPC8544_I2C_IRQ 43
+#define MPC85XX_ESDHC_IRQ 72
#define RTC_REGS_OFFSET 0x68
#define PLATFORM_CLK_FREQ_HZ (400 * 1000 * 1000)
@@ -203,6 +208,22 @@ static void dt_i2c_create(void *fdt, const char *soc, const char *mpic,
g_free(i2c);
}
+static void dt_sdhc_create(void *fdt, const char *parent, const char *mpic)
+{
+ hwaddr mmio = MPC85XX_ESDHC_REGS_OFFSET;
+ hwaddr size = MPC85XX_ESDHC_REGS_SIZE;
+ int irq = MPC85XX_ESDHC_IRQ;
+ g_autofree char *name = NULL;
+
+ name = g_strdup_printf("%s/sdhc@%" PRIx64, parent, mmio);
+ qemu_fdt_add_subnode(fdt, name);
+ qemu_fdt_setprop(fdt, name, "sdhci,auto-cmd12", NULL, 0);
+ qemu_fdt_setprop_phandle(fdt, name, "interrupt-parent", mpic);
+ qemu_fdt_setprop_cells(fdt, name, "bus-width", 4);
+ qemu_fdt_setprop_cells(fdt, name, "interrupts", irq, 0x2);
+ qemu_fdt_setprop_cells(fdt, name, "reg", mmio, size);
+ qemu_fdt_setprop_string(fdt, name, "compatible", "fsl,esdhc");
+}
typedef struct PlatformDevtreeData {
void *fdt;
@@ -553,6 +574,10 @@ static int ppce500_load_device_tree(PPCE500MachineState *pms,
dt_rtc_create(fdt, "i2c", "rtc");
+ /* sdhc */
+ if (pmc->has_esdhc) {
+ dt_sdhc_create(fdt, soc, mpic);
+ }
gutil = g_strdup_printf("%s/global-utilities@%llx", soc,
MPC8544_UTIL_OFFSET);
@@ -982,7 +1007,8 @@ void ppce500_init(MachineState *machine)
0, qdev_get_gpio_in(mpicdev, 42), 399193,
serial_hd(1), DEVICE_BIG_ENDIAN);
}
- /* I2C */
+
+ /* I2C */
dev = qdev_new("mpc-i2c");
s = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(s, &error_fatal);
@@ -992,6 +1018,26 @@ void ppce500_init(MachineState *machine)
i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
i2c_slave_create_simple(i2c, "ds1338", RTC_REGS_OFFSET);
+ /* eSDHC */
+ if (pmc->has_esdhc) {
+ uint64_t sdhci_regsize;
+
+ dev = qdev_new(TYPE_SYSBUS_SDHCI);
+ /*
+ * Compatible with:
+ * - SD Host Controller Specification Version 2.0 Part A2
+ */
+ qdev_prop_set_uint8(dev, "sd-spec-version", 2);
+ s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
+ sysbus_mmio_map(s, 0, pmc->ccsrbar_base + MPC85XX_ESDHC_REGS_OFFSET);
+ sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC85XX_ESDHC_IRQ));
+ sdhci_regsize = memory_region_size(sysbus_mmio_get_region(s, 0));
+ create_unimplemented_device("esdhc",
+ pmc->ccsrbar_base
+ + MPC85XX_ESDHC_REGS_OFFSET + sdhci_regsize,
+ MPC85XX_ESDHC_REGS_SIZE - sdhci_regsize);
+ }
/* General Utility device */
dev = qdev_new("mpc8544-guts");
diff --git a/hw/ppc/e500.h b/hw/ppc/e500.h
index 68f754ce50..8c09ef92e4 100644
--- a/hw/ppc/e500.h
+++ b/hw/ppc/e500.h
@@ -27,6 +27,7 @@ struct PPCE500MachineClass {
int mpic_version;
bool has_mpc8xxx_gpio;
+ bool has_esdhc;
hwaddr platform_bus_base;
hwaddr platform_bus_size;
int platform_bus_first_irq;
diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c
index 5bb1c603da..44bf874b0f 100644
--- a/hw/ppc/e500plat.c
+++ b/hw/ppc/e500plat.c
@@ -86,6 +86,7 @@ static void e500plat_machine_class_init(ObjectClass *oc, void *data)
pmc->fixup_devtree = e500plat_fixup_devtree;
pmc->mpic_version = OPENPIC_MODEL_FSL_MPIC_42;
pmc->has_mpc8xxx_gpio = true;
+ pmc->has_esdhc = true;
pmc->platform_bus_base = 0xf00000000ULL;
pmc->platform_bus_size = 128 * MiB;
pmc->platform_bus_first_irq = 5;
--
2.37.3
next prev parent reply other threads:[~2022-10-31 11:56 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-31 11:53 [PATCH v5 0/6] ppc/e500: Add support for two types of flash, cleanup Philippe Mathieu-Daudé
2022-10-31 11:53 ` [PATCH v5 1/6] hw/sd/sdhci: MMIO region is implemented in 32-bit accesses Philippe Mathieu-Daudé
2022-11-01 22:32 ` Bernhard Beschow
2022-10-31 11:53 ` [RFC PATCH v5 2/6] hw/sd/sdhci: Map host controller interface in host endianess Philippe Mathieu-Daudé
2022-10-31 15:28 ` Philippe Mathieu-Daudé
2022-10-31 11:53 ` [PATCH v5 3/6] hw/block/pflash_cfi0{1, 2}: Error out if device length isn't a power of two Philippe Mathieu-Daudé
2022-10-31 11:54 ` [PATCH v5 4/6] docs/system/ppc/ppce500: Use qemu-system-ppc64 across the board(s) Philippe Mathieu-Daudé
2022-10-31 11:54 ` [PATCH v5 5/6] hw/ppc/e500: Implement pflash handling Philippe Mathieu-Daudé
2022-10-31 11:54 ` Philippe Mathieu-Daudé [this message]
2022-10-31 15:12 ` [PATCH v5 6/6] hw/ppc/e500: Add Freescale eSDHC to e500plat Philippe Mathieu-Daudé
2022-10-31 15:19 ` Philippe Mathieu-Daudé
2022-11-01 10:37 ` Bernhard Beschow
2022-11-01 10:41 ` [PATCH v5 0/6] ppc/e500: Add support for two types of flash, cleanup Bernhard Beschow
2022-11-01 16:01 ` Bernhard Beschow
2022-11-01 16:58 ` Philippe Mathieu-Daudé
2022-11-01 17:43 ` Philippe Mathieu-Daudé
2022-11-01 17:56 ` Philippe Mathieu-Daudé
2022-11-01 19:37 ` B
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