From: "Michael S. Tsirkin" <mst@redhat.com>
To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>,
Jason Wang <jasowang@redhat.com>, Peter Xu <peterx@redhat.com>,
Yi Liu <yi.l.liu@intel.com>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Richard Henderson <richard.henderson@linaro.org>,
Eduardo Habkost <eduardo@habkost.net>
Subject: [PULL v2 80/82] intel-iommu: drop VTDBus
Date: Wed, 2 Nov 2022 12:12:13 -0400 [thread overview]
Message-ID: <20221102160336.616599-81-mst@redhat.com> (raw)
In-Reply-To: <20221102160336.616599-1-mst@redhat.com>
From: Jason Wang <jasowang@redhat.com>
We introduce VTDBus structure as an intermediate step for searching
the address space. This works well with SID based matching/lookup. But
when we want to support SID plus PASID based address space lookup,
this intermediate steps turns out to be a burden. So the patch simply
drops the VTDBus structure and use the PCIBus and devfn as the key for
the g_hash_table(). This simplifies the codes and the future PASID
extension.
To prevent being slower for past vtd_find_as_from_bus_num() callers, a
vtd_as cache indexed by the bus number is introduced to store the last
recent search result of a vtd_as belongs to a specific bus.
Reviewed-by: Peter Xu <peterx@redhat.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20221028061436.30093-3-jasowang@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
---
include/hw/i386/intel_iommu.h | 11 +-
hw/i386/intel_iommu.c | 234 +++++++++++++++++-----------------
2 files changed, 118 insertions(+), 127 deletions(-)
diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h
index 67653b0f9b..e49fff2a6c 100644
--- a/include/hw/i386/intel_iommu.h
+++ b/include/hw/i386/intel_iommu.h
@@ -58,7 +58,6 @@ typedef struct VTDContextEntry VTDContextEntry;
typedef struct VTDContextCacheEntry VTDContextCacheEntry;
typedef struct VTDAddressSpace VTDAddressSpace;
typedef struct VTDIOTLBEntry VTDIOTLBEntry;
-typedef struct VTDBus VTDBus;
typedef union VTD_IR_TableEntry VTD_IR_TableEntry;
typedef union VTD_IR_MSIAddress VTD_IR_MSIAddress;
typedef struct VTDPASIDDirEntry VTDPASIDDirEntry;
@@ -111,12 +110,6 @@ struct VTDAddressSpace {
IOVATree *iova_tree; /* Traces mapped IOVA ranges */
};
-struct VTDBus {
- PCIBus* bus; /* A reference to the bus to provide translation for */
- /* A table of VTDAddressSpace objects indexed by devfn */
- VTDAddressSpace *dev_as[];
-};
-
struct VTDIOTLBEntry {
uint64_t gfn;
uint16_t domain_id;
@@ -253,8 +246,8 @@ struct IntelIOMMUState {
uint32_t context_cache_gen; /* Should be in [1,MAX] */
GHashTable *iotlb; /* IOTLB */
- GHashTable *vtd_as_by_busptr; /* VTDBus objects indexed by PCIBus* reference */
- VTDBus *vtd_as_by_bus_num[VTD_PCI_BUS_MAX]; /* VTDBus objects indexed by bus number */
+ GHashTable *vtd_address_spaces; /* VTD address spaces */
+ VTDAddressSpace *vtd_as_cache[VTD_PCI_BUS_MAX]; /* VTD address space cache */
/* list of registered notifiers */
QLIST_HEAD(, VTDAddressSpace) vtd_as_with_notifiers;
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 271de995be..9fe5a222eb 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -61,6 +61,16 @@
} \
}
+/*
+ * PCI bus number (or SID) is not reliable since the device is usaully
+ * initalized before guest can configure the PCI bridge
+ * (SECONDARY_BUS_NUMBER).
+ */
+struct vtd_as_key {
+ PCIBus *bus;
+ uint8_t devfn;
+};
+
static void vtd_address_space_refresh_all(IntelIOMMUState *s);
static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n);
@@ -210,6 +220,27 @@ static guint vtd_uint64_hash(gconstpointer v)
return (guint)*(const uint64_t *)v;
}
+static gboolean vtd_as_equal(gconstpointer v1, gconstpointer v2)
+{
+ const struct vtd_as_key *key1 = v1;
+ const struct vtd_as_key *key2 = v2;
+
+ return (key1->bus == key2->bus) && (key1->devfn == key2->devfn);
+}
+
+/*
+ * Note that we use pointer to PCIBus as the key, so hashing/shifting
+ * based on the pointer value is intended. Note that we deal with
+ * collisions through vtd_as_equal().
+ */
+static guint vtd_as_hash(gconstpointer v)
+{
+ const struct vtd_as_key *key = v;
+ guint value = (guint)(uintptr_t)key->bus;
+
+ return (guint)(value << 8 | key->devfn);
+}
+
static gboolean vtd_hash_remove_by_domain(gpointer key, gpointer value,
gpointer user_data)
{
@@ -248,22 +279,14 @@ static gboolean vtd_hash_remove_by_page(gpointer key, gpointer value,
static void vtd_reset_context_cache_locked(IntelIOMMUState *s)
{
VTDAddressSpace *vtd_as;
- VTDBus *vtd_bus;
- GHashTableIter bus_it;
- uint32_t devfn_it;
+ GHashTableIter as_it;
trace_vtd_context_cache_reset();
- g_hash_table_iter_init(&bus_it, s->vtd_as_by_busptr);
+ g_hash_table_iter_init(&as_it, s->vtd_address_spaces);
- while (g_hash_table_iter_next (&bus_it, NULL, (void**)&vtd_bus)) {
- for (devfn_it = 0; devfn_it < PCI_DEVFN_MAX; ++devfn_it) {
- vtd_as = vtd_bus->dev_as[devfn_it];
- if (!vtd_as) {
- continue;
- }
- vtd_as->context_cache_entry.context_cache_gen = 0;
- }
+ while (g_hash_table_iter_next (&as_it, NULL, (void**)&vtd_as)) {
+ vtd_as->context_cache_entry.context_cache_gen = 0;
}
s->context_cache_gen = 1;
}
@@ -993,32 +1016,6 @@ static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, uint32_t level)
return slpte & rsvd_mask;
}
-/* Find the VTD address space associated with a given bus number */
-static VTDBus *vtd_find_as_from_bus_num(IntelIOMMUState *s, uint8_t bus_num)
-{
- VTDBus *vtd_bus = s->vtd_as_by_bus_num[bus_num];
- GHashTableIter iter;
-
- if (vtd_bus) {
- return vtd_bus;
- }
-
- /*
- * Iterate over the registered buses to find the one which
- * currently holds this bus number and update the bus_num
- * lookup table.
- */
- g_hash_table_iter_init(&iter, s->vtd_as_by_busptr);
- while (g_hash_table_iter_next(&iter, NULL, (void **)&vtd_bus)) {
- if (pci_bus_num(vtd_bus->bus) == bus_num) {
- s->vtd_as_by_bus_num[bus_num] = vtd_bus;
- return vtd_bus;
- }
- }
-
- return NULL;
-}
-
/* Given the @iova, get relevant @slptep. @slpte_level will be the last level
* of the translation, can be used for deciding the size of large page.
*/
@@ -1632,26 +1629,15 @@ static bool vtd_switch_address_space(VTDAddressSpace *as)
static void vtd_switch_address_space_all(IntelIOMMUState *s)
{
+ VTDAddressSpace *vtd_as;
GHashTableIter iter;
- VTDBus *vtd_bus;
- int i;
- g_hash_table_iter_init(&iter, s->vtd_as_by_busptr);
- while (g_hash_table_iter_next(&iter, NULL, (void **)&vtd_bus)) {
- for (i = 0; i < PCI_DEVFN_MAX; i++) {
- if (!vtd_bus->dev_as[i]) {
- continue;
- }
- vtd_switch_address_space(vtd_bus->dev_as[i]);
- }
+ g_hash_table_iter_init(&iter, s->vtd_address_spaces);
+ while (g_hash_table_iter_next(&iter, NULL, (void **)&vtd_as)) {
+ vtd_switch_address_space(vtd_as);
}
}
-static inline uint16_t vtd_make_source_id(uint8_t bus_num, uint8_t devfn)
-{
- return ((bus_num & 0xffUL) << 8) | (devfn & 0xffUL);
-}
-
static const bool vtd_qualified_faults[] = {
[VTD_FR_RESERVED] = false,
[VTD_FR_ROOT_ENTRY_P] = false,
@@ -1686,18 +1672,37 @@ static inline bool vtd_is_interrupt_addr(hwaddr addr)
return VTD_INTERRUPT_ADDR_FIRST <= addr && addr <= VTD_INTERRUPT_ADDR_LAST;
}
+static gboolean vtd_find_as_by_sid(gpointer key, gpointer value,
+ gpointer user_data)
+{
+ struct vtd_as_key *as_key = (struct vtd_as_key *)key;
+ uint16_t target_sid = *(uint16_t *)user_data;
+ uint16_t sid = PCI_BUILD_BDF(pci_bus_num(as_key->bus), as_key->devfn);
+ return sid == target_sid;
+}
+
+static VTDAddressSpace *vtd_get_as_by_sid(IntelIOMMUState *s, uint16_t sid)
+{
+ uint8_t bus_num = PCI_BUS_NUM(sid);
+ VTDAddressSpace *vtd_as = s->vtd_as_cache[bus_num];
+
+ if (vtd_as &&
+ (sid == PCI_BUILD_BDF(pci_bus_num(vtd_as->bus), vtd_as->devfn))) {
+ return vtd_as;
+ }
+
+ vtd_as = g_hash_table_find(s->vtd_address_spaces, vtd_find_as_by_sid, &sid);
+ s->vtd_as_cache[bus_num] = vtd_as;
+
+ return vtd_as;
+}
+
static void vtd_pt_enable_fast_path(IntelIOMMUState *s, uint16_t source_id)
{
- VTDBus *vtd_bus;
VTDAddressSpace *vtd_as;
bool success = false;
- vtd_bus = vtd_find_as_from_bus_num(s, VTD_SID_TO_BUS(source_id));
- if (!vtd_bus) {
- goto out;
- }
-
- vtd_as = vtd_bus->dev_as[VTD_SID_TO_DEVFN(source_id)];
+ vtd_as = vtd_get_as_by_sid(s, source_id);
if (!vtd_as) {
goto out;
}
@@ -1733,7 +1738,7 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,
VTDContextCacheEntry *cc_entry;
uint64_t slpte, page_mask;
uint32_t level;
- uint16_t source_id = vtd_make_source_id(bus_num, devfn);
+ uint16_t source_id = PCI_BUILD_BDF(bus_num, devfn);
int ret_fr;
bool is_fpd_set = false;
bool reads = true;
@@ -1905,11 +1910,10 @@ static void vtd_context_device_invalidate(IntelIOMMUState *s,
uint16_t source_id,
uint16_t func_mask)
{
+ GHashTableIter as_it;
uint16_t mask;
- VTDBus *vtd_bus;
VTDAddressSpace *vtd_as;
uint8_t bus_n, devfn;
- uint16_t devfn_it;
trace_vtd_inv_desc_cc_devices(source_id, func_mask);
@@ -1932,32 +1936,31 @@ static void vtd_context_device_invalidate(IntelIOMMUState *s,
mask = ~mask;
bus_n = VTD_SID_TO_BUS(source_id);
- vtd_bus = vtd_find_as_from_bus_num(s, bus_n);
- if (vtd_bus) {
- devfn = VTD_SID_TO_DEVFN(source_id);
- for (devfn_it = 0; devfn_it < PCI_DEVFN_MAX; ++devfn_it) {
- vtd_as = vtd_bus->dev_as[devfn_it];
- if (vtd_as && ((devfn_it & mask) == (devfn & mask))) {
- trace_vtd_inv_desc_cc_device(bus_n, VTD_PCI_SLOT(devfn_it),
- VTD_PCI_FUNC(devfn_it));
- vtd_iommu_lock(s);
- vtd_as->context_cache_entry.context_cache_gen = 0;
- vtd_iommu_unlock(s);
- /*
- * Do switch address space when needed, in case if the
- * device passthrough bit is switched.
- */
- vtd_switch_address_space(vtd_as);
- /*
- * So a device is moving out of (or moving into) a
- * domain, resync the shadow page table.
- * This won't bring bad even if we have no such
- * notifier registered - the IOMMU notification
- * framework will skip MAP notifications if that
- * happened.
- */
- vtd_sync_shadow_page_table(vtd_as);
- }
+ devfn = VTD_SID_TO_DEVFN(source_id);
+
+ g_hash_table_iter_init(&as_it, s->vtd_address_spaces);
+ while (g_hash_table_iter_next(&as_it, NULL, (void**)&vtd_as)) {
+ if ((pci_bus_num(vtd_as->bus) == bus_n) &&
+ (vtd_as->devfn & mask) == (devfn & mask)) {
+ trace_vtd_inv_desc_cc_device(bus_n, VTD_PCI_SLOT(vtd_as->devfn),
+ VTD_PCI_FUNC(vtd_as->devfn));
+ vtd_iommu_lock(s);
+ vtd_as->context_cache_entry.context_cache_gen = 0;
+ vtd_iommu_unlock(s);
+ /*
+ * Do switch address space when needed, in case if the
+ * device passthrough bit is switched.
+ */
+ vtd_switch_address_space(vtd_as);
+ /*
+ * So a device is moving out of (or moving into) a
+ * domain, resync the shadow page table.
+ * This won't bring bad even if we have no such
+ * notifier registered - the IOMMU notification
+ * framework will skip MAP notifications if that
+ * happened.
+ */
+ vtd_sync_shadow_page_table(vtd_as);
}
}
}
@@ -2473,18 +2476,13 @@ static bool vtd_process_device_iotlb_desc(IntelIOMMUState *s,
{
VTDAddressSpace *vtd_dev_as;
IOMMUTLBEvent event;
- struct VTDBus *vtd_bus;
hwaddr addr;
uint64_t sz;
uint16_t sid;
- uint8_t devfn;
bool size;
- uint8_t bus_num;
addr = VTD_INV_DESC_DEVICE_IOTLB_ADDR(inv_desc->hi);
sid = VTD_INV_DESC_DEVICE_IOTLB_SID(inv_desc->lo);
- devfn = sid & 0xff;
- bus_num = sid >> 8;
size = VTD_INV_DESC_DEVICE_IOTLB_SIZE(inv_desc->hi);
if ((inv_desc->lo & VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO) ||
@@ -2495,12 +2493,11 @@ static bool vtd_process_device_iotlb_desc(IntelIOMMUState *s,
return false;
}
- vtd_bus = vtd_find_as_from_bus_num(s, bus_num);
- if (!vtd_bus) {
- goto done;
- }
-
- vtd_dev_as = vtd_bus->dev_as[devfn];
+ /*
+ * Using sid is OK since the guest should have finished the
+ * initialization of both the bus and device.
+ */
+ vtd_dev_as = vtd_get_as_by_sid(s, sid);
if (!vtd_dev_as) {
goto done;
}
@@ -3427,27 +3424,27 @@ static const MemoryRegionOps vtd_mem_ir_ops = {
VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn)
{
- uintptr_t key = (uintptr_t)bus;
- VTDBus *vtd_bus = g_hash_table_lookup(s->vtd_as_by_busptr, &key);
+ /*
+ * We can't simply use sid here since the bus number might not be
+ * initialized by the guest.
+ */
+ struct vtd_as_key key = {
+ .bus = bus,
+ .devfn = devfn,
+ };
VTDAddressSpace *vtd_dev_as;
char name[128];
- if (!vtd_bus) {
- uintptr_t *new_key = g_malloc(sizeof(*new_key));
- *new_key = (uintptr_t)bus;
- /* No corresponding free() */
- vtd_bus = g_malloc0(sizeof(VTDBus) + sizeof(VTDAddressSpace *) * \
- PCI_DEVFN_MAX);
- vtd_bus->bus = bus;
- g_hash_table_insert(s->vtd_as_by_busptr, new_key, vtd_bus);
- }
-
- vtd_dev_as = vtd_bus->dev_as[devfn];
-
+ vtd_dev_as = g_hash_table_lookup(s->vtd_address_spaces, &key);
if (!vtd_dev_as) {
+ struct vtd_as_key *new_key = g_malloc(sizeof(*new_key));
+
+ new_key->bus = bus;
+ new_key->devfn = devfn;
+
snprintf(name, sizeof(name), "vtd-%02x.%x", PCI_SLOT(devfn),
PCI_FUNC(devfn));
- vtd_bus->dev_as[devfn] = vtd_dev_as = g_new0(VTDAddressSpace, 1);
+ vtd_dev_as = g_new0(VTDAddressSpace, 1);
vtd_dev_as->bus = bus;
vtd_dev_as->devfn = (uint8_t)devfn;
@@ -3503,6 +3500,8 @@ VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn)
&vtd_dev_as->nodmar, 0);
vtd_switch_address_space(vtd_dev_as);
+
+ g_hash_table_insert(s->vtd_address_spaces, new_key, vtd_dev_as);
}
return vtd_dev_as;
}
@@ -3881,7 +3880,6 @@ static void vtd_realize(DeviceState *dev, Error **errp)
QLIST_INIT(&s->vtd_as_with_notifiers);
qemu_mutex_init(&s->iommu_lock);
- memset(s->vtd_as_by_bus_num, 0, sizeof(s->vtd_as_by_bus_num));
memory_region_init_io(&s->csrmem, OBJECT(s), &vtd_mem_ops, s,
"intel_iommu", DMAR_REG_SIZE);
@@ -3903,8 +3901,8 @@ static void vtd_realize(DeviceState *dev, Error **errp)
/* No corresponding destroy */
s->iotlb = g_hash_table_new_full(vtd_uint64_hash, vtd_uint64_equal,
g_free, g_free);
- s->vtd_as_by_busptr = g_hash_table_new_full(vtd_uint64_hash, vtd_uint64_equal,
- g_free, g_free);
+ s->vtd_address_spaces = g_hash_table_new_full(vtd_as_hash, vtd_as_equal,
+ g_free, g_free);
vtd_init(s);
sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, Q35_HOST_BRIDGE_IOMMU_ADDR);
pci_setup_iommu(bus, vtd_host_dma_iommu, dev);
--
MST
next prev parent reply other threads:[~2022-11-02 16:20 UTC|newest]
Thread overview: 113+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-02 16:02 [PULL v2 00/82] pci,pc,virtio: features, tests, fixes, cleanups Michael S. Tsirkin
2022-11-02 16:08 ` [PULL v2 01/82] hw/i386/e820: remove legacy reserved entries for e820 Michael S. Tsirkin
2022-11-02 16:08 ` [PULL v2 02/82] tests/acpi: allow SSDT changes Michael S. Tsirkin
2022-11-02 16:08 ` [PULL v2 03/82] acpi/ssdt: Fix aml_or() and aml_and() in if clause Michael S. Tsirkin
2022-11-02 16:08 ` [PULL v2 04/82] acpi/nvdimm: define macro for NVDIMM Device _DSM Michael S. Tsirkin
2022-11-02 16:08 ` [PULL v2 05/82] acpi/nvdimm: Implement ACPI NVDIMM Label Methods Michael S. Tsirkin
2022-11-02 16:08 ` [PULL v2 06/82] test/acpi/bios-tables-test: SSDT: update golden master binaries Michael S. Tsirkin
2022-11-02 16:08 ` [PULL v2 07/82] virtio-crypto: Support asynchronous mode Michael S. Tsirkin
2022-11-02 16:08 ` [PULL v2 08/82] crypto: Support DER encodings Michael S. Tsirkin
2022-11-02 16:08 ` [PULL v2 09/82] crypto: Support export akcipher to pkcs8 Michael S. Tsirkin
2022-11-02 16:08 ` [PULL v2 10/82] cryptodev: Add a lkcf-backend for cryptodev Michael S. Tsirkin
2022-11-02 16:08 ` [PULL v2 11/82] acpi/tests/avocado/bits: initial commit of test scripts that are run by biosbits Michael S. Tsirkin
2022-11-02 16:08 ` [PULL v2 12/82] acpi/tests/avocado/bits: disable acpi PSS tests that are failing in biosbits Michael S. Tsirkin
2022-11-02 16:08 ` [PULL v2 13/82] acpi/tests/avocado/bits: add biosbits config file for running bios tests Michael S. Tsirkin
2022-11-02 16:08 ` [PULL v2 14/82] acpi/tests/avocado/bits: add acpi and smbios avocado tests that uses biosbits Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 15/82] acpi/tests/avocado/bits/doc: add a doc file to describe the acpi bits test Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 16/82] MAINTAINERS: add myself as the maintainer for acpi biosbits avocado tests Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 17/82] hw/smbios: add core_count2 to smbios table type 4 Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 18/82] bios-tables-test: teach test to use smbios 3.0 tables Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 19/82] tests/acpi: allow changes for core_count2 test Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 20/82] bios-tables-test: add test for number of cores > 255 Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 21/82] tests/acpi: update tables for new core count test Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 22/82] tests/acpi: virt: allow acpi MADT and FADT changes Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 23/82] acpi: fadt: support revision 6.0 of the ACPI specification Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 24/82] acpi: arm/virt: madt: bump to revision 4 accordingly to ACPI 6.0 Errata A Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 25/82] tests/acpi: virt: update ACPI MADT and FADT binaries Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 26/82] hw/pci: PCIe Data Object Exchange emulation Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 27/82] hw/mem/cxl-type3: Add MSIX support Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 28/82] hw/cxl/cdat: CXL CDAT Data Object Exchange implementation Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 29/82] hw/mem/cxl-type3: Add CXL CDAT Data Object Exchange Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 30/82] hw/pci-bridge/cxl-upstream: Add a CDAT table access DOE Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 31/82] vhost: Change the sequence of device start Michael S. Tsirkin
2022-11-05 16:35 ` Bernhard Beschow
2022-11-05 16:43 ` Michael S. Tsirkin
2022-11-06 18:00 ` Christian A. Ehrhardt
2022-11-07 13:30 ` Michael S. Tsirkin
2022-11-07 17:31 ` Christian A. Ehrhardt
2022-11-07 17:54 ` Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 32/82] vhost-user: Support vhost_dev_start Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 33/82] hw/virtio/virtio-iommu-pci: Enforce the device is plugged on the root bus Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 34/82] virtio: re-order vm_running and use_started checks Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 35/82] virtio: introduce __virtio_queue_reset() Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 36/82] virtio: introduce virtio_queue_reset() Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 37/82] virtio: introduce virtio_queue_enable() Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 38/82] virtio: core: vq reset feature negotation support Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 39/82] virtio-pci: support queue reset Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 40/82] virtio-pci: support queue enable Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 41/82] vhost: expose vhost_virtqueue_start() Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 42/82] vhost: expose vhost_virtqueue_stop() Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 43/82] vhost-net: vhost-kernel: introduce vhost_net_virtqueue_reset() Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 44/82] vhost-net: vhost-kernel: introduce vhost_net_virtqueue_restart() Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 45/82] virtio-net: introduce flush_or_purge_queued_packets() Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 46/82] virtio-net: support queue reset Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 47/82] virtio-net: support queue_enable Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 48/82] vhost: vhost-kernel: enable vq reset feature Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 49/82] virtio-net: " Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 50/82] virtio-rng-pci: Allow setting nvectors, so we can use MSI-X Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 51/82] vhost-user: Fix out of order vring host notification handling Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 52/82] acpi: pc: vga: use AcpiDevAmlIf interface to build VGA device descriptors Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 53/82] tests: acpi: whitelist DSDT before generating PCI-ISA bridge AML automatically Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 54/82] acpi: pc/q35: drop ad-hoc PCI-ISA bridge AML routines and let bus ennumeration generate AML Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 55/82] tests: acpi: update expected DSDT after ISA bridge is moved directly under PCI host bridge Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 56/82] tests: acpi: whitelist DSDT before generating ICH9_SMB AML automatically Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 57/82] acpi: add get_dev_aml_func() helper Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 58/82] acpi: enumerate SMB bridge automatically along with other PCI devices Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 59/82] tests: acpi: update expected blobs Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 60/82] tests: acpi: pc/q35 whitelist DSDT before \_GPE cleanup Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 61/82] acpi: pc/35: sanitize _GPE declaration order Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 62/82] tests: acpi: update expected blobs Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 63/82] hw/acpi/erst.c: Fix memory handling issues Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 64/82] MAINTAINERS: Add qapi/virtio.json to section "virtio" Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 65/82] msix: Assert that specified vector is in range Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 66/82] hw/i386/pc.c: CXL Fixed Memory Window should not reserve e820 in bios Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 67/82] hw/i386/acpi-build: Remove unused struct Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 68/82] hw/i386/acpi-build: Resolve redundant attribute Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 69/82] hw/i386/acpi-build: Resolve north rather than south bridges Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 70/82] hmat acpi: Don't require initiator value in -numa Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 71/82] tests: acpi: add and whitelist *.hmat-noinitiator expected blobs Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 72/82] tests: acpi: q35: add test for hmat nodes without initiators Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 73/82] tests: acpi: q35: update expected blobs *.hmat-noinitiators expected HMAT: Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 74/82] tests: Add HMAT AArch64/virt empty table files Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 75/82] hw/arm/virt: Enable HMAT on arm virt machine Michael S. Tsirkin
2022-11-02 16:12 ` [PULL v2 76/82] tests: acpi: aarch64/virt: add a test for hmat nodes with no initiators Michael S. Tsirkin
2022-11-02 16:12 ` [PULL v2 77/82] tests: virt: Update expected *.acpihmatvirt tables Michael S. Tsirkin
2022-11-02 16:12 ` [PULL v2 78/82] vfio: move implement of vfio_get_xlat_addr() to memory.c Michael S. Tsirkin
2022-11-02 16:12 ` [PULL v2 79/82] intel-iommu: don't warn guest errors when getting rid2pasid entry Michael S. Tsirkin
2022-11-02 16:12 ` Michael S. Tsirkin [this message]
2022-11-02 16:12 ` [PULL v2 81/82] intel-iommu: convert VTD_PE_GET_FPD_ERR() to be a function Michael S. Tsirkin
2022-11-02 16:12 ` [PULL v2 82/82] intel-iommu: PASID support Michael S. Tsirkin
2022-11-02 19:47 ` [PULL v2 00/82] pci,pc,virtio: features, tests, fixes, cleanups Stefan Hajnoczi
2022-11-03 12:13 ` Michael S. Tsirkin
2022-11-03 13:29 ` Stefan Hajnoczi
2022-11-03 14:54 ` Michael S. Tsirkin
2022-11-03 21:59 ` Michael S. Tsirkin
2022-11-03 13:31 ` Philippe Mathieu-Daudé
2022-11-03 15:42 ` Ani Sinha
2022-11-03 15:49 ` Stefan Hajnoczi
2022-11-03 15:58 ` Michael S. Tsirkin
2022-11-03 16:27 ` Stefan Hajnoczi
2022-11-03 15:59 ` Daniel P. Berrangé
2022-11-03 16:25 ` Stefan Hajnoczi
2022-11-03 16:38 ` Daniel P. Berrangé
2022-11-03 16:47 ` Peter Maydell
2022-11-03 16:49 ` Daniel P. Berrangé
2022-11-03 17:05 ` Stefan Hajnoczi
2022-11-03 16:47 ` Daniel P. Berrangé
2022-11-03 16:47 ` Ani Sinha
2022-11-03 16:48 ` Ani Sinha
2022-11-03 16:56 ` Ani Sinha
2022-11-03 17:41 ` Daniel P. Berrangé
2022-11-03 17:44 ` Ani Sinha
2022-11-03 20:32 ` Michael S. Tsirkin
2022-11-04 3:07 ` Ani Sinha
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20221102160336.616599-81-mst@redhat.com \
--to=mst@redhat.com \
--cc=eduardo@habkost.net \
--cc=jasowang@redhat.com \
--cc=marcel.apfelbaum@gmail.com \
--cc=pbonzini@redhat.com \
--cc=peter.maydell@linaro.org \
--cc=peterx@redhat.com \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
--cc=yi.l.liu@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).