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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id g17-20020a5d4891000000b0023655e51c33sm3255743wrq.4.2022.11.04.04.35.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Nov 2022 04:35:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 0/7] target-arm queue Date: Fri, 4 Nov 2022 11:35:08 +0000 Message-Id: <20221104113515.2278508-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi; this pull request has a collection of bug fixes for rc0. The big one is the trusted firmware boot regression fix. thanks -- PMM The following changes since commit ece5f8374d0416a339f0c0a9399faa2c42d4ad6f: Merge tag 'linux-user-for-7.2-pull-request' of https://gitlab.com/laurent_vivier/qemu into staging (2022-11-03 10:55:05 -0400) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20221104 for you to fetch changes up to cead7fa4c06087c86c67c5ce815cc1ff0bfeac3a: target/arm: Two fixes for secure ptw (2022-11-04 10:58:58 +0000) ---------------------------------------------------------------- target-arm queue: * Fix regression booting Trusted Firmware * Honor HCR_E2H and HCR_TGE in ats_write64() * Copy the entire vector in DO_ZIP * Fix Privileged Access Never (PAN) for aarch32 * Make TLBIOS and TLBIRANGE ops trap on HCR_EL2.TTLB * Set SCR_EL3.HXEn when direct booting kernel * Set SME and SVE EL3 vector lengths when direct booting kernel ---------------------------------------------------------------- Ake Koomsin (1): target/arm: Honor HCR_E2H and HCR_TGE in ats_write64() Peter Maydell (3): hw/arm/boot: Set SME and SVE EL3 vector lengths when booting kernel hw/arm/boot: Set SCR_EL3.HXEn when booting kernel target/arm: Make TLBIOS and TLBIRANGE ops trap on HCR_EL2.TTLB Richard Henderson (2): target/arm: Copy the entire vector in DO_ZIP target/arm: Two fixes for secure ptw Timofey Kutergin (1): target/arm: Fix Privileged Access Never (PAN) for aarch32 hw/arm/boot.c | 5 ++++ target/arm/helper.c | 64 +++++++++++++++++++++++++++++-------------------- target/arm/ptw.c | 50 ++++++++++++++++++++++++++++---------- target/arm/sve_helper.c | 4 ++-- 4 files changed, 83 insertions(+), 40 deletions(-)