From: "Alex Bennée" <alex.bennee@linaro.org>
To: qemu-devel@nongnu.org
Cc: f4bug@amsat.org, "Alex Bennée" <alex.bennee@linaro.org>,
"Wenchao Wang" <wenchao.wang@intel.com>,
"Kamil Rytarowski" <kamil@netbsd.org>,
"Reinoud Zandijk" <reinoud@netbsd.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Marcelo Tosatti" <mtosatti@redhat.com>,
"Sunil Muthuswamy" <sunilmut@microsoft.com>,
haxm-team@intel.com (open list:X86 HAXM CPUs),
kvm@vger.kernel.org (open list:X86 KVM CPUs)
Subject: [PATCH v5 13/20] target/i386: add explicit initialisation for MexTxAttrs
Date: Fri, 11 Nov 2022 18:25:28 +0000 [thread overview]
Message-ID: <20221111182535.64844-14-alex.bennee@linaro.org> (raw)
In-Reply-To: <20221111182535.64844-1-alex.bennee@linaro.org>
Where appropriate initialise with MEMTXATTRS_CPU otherwise use
MEMTXATTRS_UNSPECIFIED instead of the null initialiser.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
target/i386/cpu.h | 4 +++-
target/i386/hax/hax-all.c | 2 +-
target/i386/nvmm/nvmm-all.c | 2 +-
target/i386/sev.c | 2 +-
target/i386/whpx/whpx-all.c | 2 +-
5 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index d4bc19577a..04ab96b076 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2246,7 +2246,9 @@ static inline uint32_t cpu_compute_eflags(CPUX86State *env)
static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env)
{
- return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 });
+ MemTxAttrs attrs = MEMTXATTRS_CPU(env_cpu(env));
+ attrs.secure = (env->hflags & HF_SMM_MASK) != 0;
+ return attrs;
}
static inline int32_t x86_get_a20_mask(CPUX86State *env)
diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c
index b185ee8de4..337090e16f 100644
--- a/target/i386/hax/hax-all.c
+++ b/target/i386/hax/hax-all.c
@@ -385,7 +385,7 @@ static int hax_handle_io(CPUArchState *env, uint32_t df, uint16_t port,
{
uint8_t *ptr;
int i;
- MemTxAttrs attrs = { 0 };
+ MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
if (!df) {
ptr = (uint8_t *) buffer;
diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c
index b75738ee9c..cb0720a6fa 100644
--- a/target/i386/nvmm/nvmm-all.c
+++ b/target/i386/nvmm/nvmm-all.c
@@ -502,7 +502,7 @@ nvmm_vcpu_post_run(CPUState *cpu, struct nvmm_vcpu_exit *exit)
static void
nvmm_io_callback(struct nvmm_io *io)
{
- MemTxAttrs attrs = { 0 };
+ MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
int ret;
ret = address_space_rw(&address_space_io, io->port, attrs, io->data,
diff --git a/target/i386/sev.c b/target/i386/sev.c
index 32f7dbac4e..292cbcdd92 100644
--- a/target/i386/sev.c
+++ b/target/i386/sev.c
@@ -1274,7 +1274,7 @@ bool sev_add_kernel_loader_hashes(SevKernelLoaderContext *ctx, Error **errp)
uint8_t *hashp;
size_t hash_len = HASH_SIZE;
hwaddr mapped_len = sizeof(*padded_ht);
- MemTxAttrs attrs = { 0 };
+ MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
bool ret = true;
/*
diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c
index e738d83e81..42846144dd 100644
--- a/target/i386/whpx/whpx-all.c
+++ b/target/i386/whpx/whpx-all.c
@@ -791,7 +791,7 @@ static HRESULT CALLBACK whpx_emu_ioport_callback(
void *ctx,
WHV_EMULATOR_IO_ACCESS_INFO *IoAccess)
{
- MemTxAttrs attrs = { 0 };
+ MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
address_space_rw(&address_space_io, IoAccess->Port, attrs,
&IoAccess->Data, IoAccess->AccessSize,
IoAccess->Direction);
--
2.34.1
next prev parent reply other threads:[~2022-11-11 18:36 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-11 18:25 [PATCH for 8.0 v5 00/20] use MemTxAttrs to avoid current_cpu in hw/ Alex Bennée
2022-11-11 18:25 ` [PATCH v5 01/20] hw: encode accessing CPU index in MemTxAttrs Alex Bennée
2022-11-12 4:18 ` Richard Henderson
2022-11-21 18:32 ` Peter Maydell
2022-11-11 18:25 ` [PATCH v5 02/20] target/arm: ensure TCG IO accesses set appropriate MemTxAttrs Alex Bennée
2022-11-12 5:17 ` Richard Henderson
2022-11-12 5:26 ` Richard Henderson
2022-11-11 18:25 ` [PATCH v5 03/20] target/arm: ensure HVF traps " Alex Bennée
2022-11-11 18:25 ` [PATCH v5 04/20] target/arm: ensure KVM " Alex Bennée
2022-11-12 5:29 ` Richard Henderson
2022-11-11 18:25 ` [PATCH v5 05/20] target/arm: ensure m-profile helpers " Alex Bennée
2022-11-12 5:26 ` Richard Henderson
2022-11-11 18:25 ` [PATCH v5 06/20] qtest: make read/write operation appear to be from CPU Alex Bennée
2022-11-11 18:25 ` [PATCH v5 07/20] hw/intc/gic: use MxTxAttrs to divine accessing CPU Alex Bennée
2022-11-11 18:25 ` [PATCH v5 08/20] hw/timer: convert mptimer access to attrs to derive cpu index Alex Bennée
2022-11-11 18:25 ` [PATCH v5 09/20] hw/arm: remove current_cpu hack from pxa2xx access Alex Bennée
2022-11-12 5:36 ` Richard Henderson
2022-11-13 19:43 ` Philippe Mathieu-Daudé
2022-11-11 18:25 ` [PATCH v5 10/20] target/microblaze: initialise MemTxAttrs for CPU access Alex Bennée
2022-11-11 19:41 ` Edgar E. Iglesias
2022-11-12 5:37 ` Richard Henderson
2022-11-13 19:44 ` Philippe Mathieu-Daudé
2022-11-11 18:25 ` [PATCH v5 11/20] target/sparc: " Alex Bennée
2022-11-12 1:02 ` Mark Cave-Ayland
2022-11-12 5:38 ` Richard Henderson
2022-11-13 19:45 ` Philippe Mathieu-Daudé
2022-11-11 18:25 ` [PATCH v5 12/20] target/riscv: " Alex Bennée
2022-11-11 18:25 ` Alex Bennée [this message]
2022-11-12 5:49 ` [PATCH v5 13/20] target/i386: add explicit initialisation for MexTxAttrs Richard Henderson
2022-11-11 18:25 ` [PATCH v5 14/20] hw/audio: explicitly set .requester_type for intel-hda Alex Bennée
2022-11-12 5:50 ` Richard Henderson
2022-11-13 19:50 ` Philippe Mathieu-Daudé
2022-11-21 18:39 ` Peter Maydell
2022-11-21 22:14 ` Philippe Mathieu-Daudé
2022-11-11 18:25 ` [PATCH v5 15/20] hw/i386: update vapic_write to use MemTxAttrs Alex Bennée
2022-11-12 5:51 ` Richard Henderson
2022-11-13 19:52 ` Philippe Mathieu-Daudé
2022-11-11 18:25 ` [PATCH v5 16/20] include: add MEMTXATTRS_MACHINE helper Alex Bennée
2022-11-12 5:52 ` Richard Henderson
2022-11-11 18:25 ` [PATCH v5 17/20] hw/intc: properly model IOAPIC MSI messages Alex Bennée
2022-11-12 5:57 ` Richard Henderson
2022-11-11 18:25 ` [PATCH v5 18/20] hw/i386: convert apic access to use MemTxAttrs Alex Bennée
2022-11-12 6:02 ` Richard Henderson
2022-11-21 18:43 ` Peter Maydell
2022-11-11 18:25 ` [PATCH v5 19/20] hw/isa: derive CPUState from MemTxAttrs in apm_ioport_writeb Alex Bennée
2022-11-12 6:04 ` Richard Henderson
2022-11-13 20:04 ` Philippe Mathieu-Daudé
2022-11-11 18:25 ` [PATCH v5 20/20] include/hw: add commentary to current_cpu export Alex Bennée
2022-11-12 6:05 ` Richard Henderson
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