From: "Alex Bennée" <alex.bennee@linaro.org>
To: qemu-devel@nongnu.org
Cc: f4bug@amsat.org, "Alex Bennée" <alex.bennee@linaro.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
qemu-arm@nongnu.org (open list:ARM TCG CPUs)
Subject: [PATCH v5 05/20] target/arm: ensure m-profile helpers set appropriate MemTxAttrs
Date: Fri, 11 Nov 2022 18:25:20 +0000 [thread overview]
Message-ID: <20221111182535.64844-6-alex.bennee@linaro.org> (raw)
In-Reply-To: <20221111182535.64844-1-alex.bennee@linaro.org>
There are a number of helpers for M-profile that deal with CPU
initiated access to the vector and stack areas. While it is unlikely
these coincided with memory mapped IO devices it is not inconceivable.
Embedded targets tend to attract all sorts of interesting code and for
completeness we should tag the transaction appropriately.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
v5
- rebase fixes for refactoring
---
target/arm/m_helper.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index 355cd4d60a..2fb1ef95cd 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -184,7 +184,7 @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value,
CPUState *cs = CPU(cpu);
CPUARMState *env = &cpu->env;
MemTxResult txres;
- GetPhysAddrResult res = {};
+ GetPhysAddrResult res = { .f.attrs = MEMTXATTRS_CPU(cs) };
ARMMMUFaultInfo fi = {};
bool secure = mmu_idx & ARM_MMU_IDX_M_S;
int exc;
@@ -272,7 +272,7 @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest, uint32_t addr,
CPUState *cs = CPU(cpu);
CPUARMState *env = &cpu->env;
MemTxResult txres;
- GetPhysAddrResult res = {};
+ GetPhysAddrResult res = { .f.attrs = MEMTXATTRS_CPU(cs) };
ARMMMUFaultInfo fi = {};
bool secure = mmu_idx & ARM_MMU_IDX_M_S;
int exc;
@@ -665,7 +665,7 @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure,
MemTxResult result;
uint32_t addr = env->v7m.vecbase[targets_secure] + exc * 4;
uint32_t vector_entry;
- MemTxAttrs attrs = {};
+ MemTxAttrs attrs = MEMTXATTRS_CPU(cs);
ARMMMUIdx mmu_idx;
bool exc_secure;
@@ -1999,7 +1999,7 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, bool secure,
CPUState *cs = CPU(cpu);
CPUARMState *env = &cpu->env;
V8M_SAttributes sattrs = {};
- GetPhysAddrResult res = {};
+ GetPhysAddrResult res = { .f.attrs = MEMTXATTRS_CPU(cs) };
ARMMMUFaultInfo fi = {};
MemTxResult txres;
@@ -2047,7 +2047,7 @@ static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMMUIdx mmu_idx,
CPUState *cs = CPU(cpu);
CPUARMState *env = &cpu->env;
MemTxResult txres;
- GetPhysAddrResult res = {};
+ GetPhysAddrResult res = { .f.attrs = MEMTXATTRS_CPU(cs) };
ARMMMUFaultInfo fi = {};
uint32_t value;
@@ -2805,7 +2805,7 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
* inspecting the other MPU state.
*/
if (arm_current_el(env) != 0 || alt) {
- GetPhysAddrResult res = {};
+ GetPhysAddrResult res = { .f.attrs = MEMTXATTRS_CPU(env_cpu(env)) };
ARMMMUFaultInfo fi = {};
/* We can ignore the return value as prot is always set */
--
2.34.1
next prev parent reply other threads:[~2022-11-11 18:27 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-11 18:25 [PATCH for 8.0 v5 00/20] use MemTxAttrs to avoid current_cpu in hw/ Alex Bennée
2022-11-11 18:25 ` [PATCH v5 01/20] hw: encode accessing CPU index in MemTxAttrs Alex Bennée
2022-11-12 4:18 ` Richard Henderson
2022-11-21 18:32 ` Peter Maydell
2022-11-11 18:25 ` [PATCH v5 02/20] target/arm: ensure TCG IO accesses set appropriate MemTxAttrs Alex Bennée
2022-11-12 5:17 ` Richard Henderson
2022-11-12 5:26 ` Richard Henderson
2022-11-11 18:25 ` [PATCH v5 03/20] target/arm: ensure HVF traps " Alex Bennée
2022-11-11 18:25 ` [PATCH v5 04/20] target/arm: ensure KVM " Alex Bennée
2022-11-12 5:29 ` Richard Henderson
2022-11-11 18:25 ` Alex Bennée [this message]
2022-11-12 5:26 ` [PATCH v5 05/20] target/arm: ensure m-profile helpers " Richard Henderson
2022-11-11 18:25 ` [PATCH v5 06/20] qtest: make read/write operation appear to be from CPU Alex Bennée
2022-11-11 18:25 ` [PATCH v5 07/20] hw/intc/gic: use MxTxAttrs to divine accessing CPU Alex Bennée
2022-11-11 18:25 ` [PATCH v5 08/20] hw/timer: convert mptimer access to attrs to derive cpu index Alex Bennée
2022-11-11 18:25 ` [PATCH v5 09/20] hw/arm: remove current_cpu hack from pxa2xx access Alex Bennée
2022-11-12 5:36 ` Richard Henderson
2022-11-13 19:43 ` Philippe Mathieu-Daudé
2022-11-11 18:25 ` [PATCH v5 10/20] target/microblaze: initialise MemTxAttrs for CPU access Alex Bennée
2022-11-11 19:41 ` Edgar E. Iglesias
2022-11-12 5:37 ` Richard Henderson
2022-11-13 19:44 ` Philippe Mathieu-Daudé
2022-11-11 18:25 ` [PATCH v5 11/20] target/sparc: " Alex Bennée
2022-11-12 1:02 ` Mark Cave-Ayland
2022-11-12 5:38 ` Richard Henderson
2022-11-13 19:45 ` Philippe Mathieu-Daudé
2022-11-11 18:25 ` [PATCH v5 12/20] target/riscv: " Alex Bennée
2022-11-11 18:25 ` [PATCH v5 13/20] target/i386: add explicit initialisation for MexTxAttrs Alex Bennée
2022-11-12 5:49 ` Richard Henderson
2022-11-11 18:25 ` [PATCH v5 14/20] hw/audio: explicitly set .requester_type for intel-hda Alex Bennée
2022-11-12 5:50 ` Richard Henderson
2022-11-13 19:50 ` Philippe Mathieu-Daudé
2022-11-21 18:39 ` Peter Maydell
2022-11-21 22:14 ` Philippe Mathieu-Daudé
2022-11-11 18:25 ` [PATCH v5 15/20] hw/i386: update vapic_write to use MemTxAttrs Alex Bennée
2022-11-12 5:51 ` Richard Henderson
2022-11-13 19:52 ` Philippe Mathieu-Daudé
2022-11-11 18:25 ` [PATCH v5 16/20] include: add MEMTXATTRS_MACHINE helper Alex Bennée
2022-11-12 5:52 ` Richard Henderson
2022-11-11 18:25 ` [PATCH v5 17/20] hw/intc: properly model IOAPIC MSI messages Alex Bennée
2022-11-12 5:57 ` Richard Henderson
2022-11-11 18:25 ` [PATCH v5 18/20] hw/i386: convert apic access to use MemTxAttrs Alex Bennée
2022-11-12 6:02 ` Richard Henderson
2022-11-21 18:43 ` Peter Maydell
2022-11-11 18:25 ` [PATCH v5 19/20] hw/isa: derive CPUState from MemTxAttrs in apm_ioport_writeb Alex Bennée
2022-11-12 6:04 ` Richard Henderson
2022-11-13 20:04 ` Philippe Mathieu-Daudé
2022-11-11 18:25 ` [PATCH v5 20/20] include/hw: add commentary to current_cpu export Alex Bennée
2022-11-12 6:05 ` Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20221111182535.64844-6-alex.bennee@linaro.org \
--to=alex.bennee@linaro.org \
--cc=f4bug@amsat.org \
--cc=peter.maydell@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).