From: "Alex Bennée" <alex.bennee@linaro.org>
To: qemu-devel@nongnu.org
Cc: f4bug@amsat.org, "Alex Bennée" <alex.bennee@linaro.org>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
qemu-arm@nongnu.org (open list:ARM cores)
Subject: [PATCH v5 08/20] hw/timer: convert mptimer access to attrs to derive cpu index
Date: Fri, 11 Nov 2022 18:25:23 +0000 [thread overview]
Message-ID: <20221111182535.64844-9-alex.bennee@linaro.org> (raw)
In-Reply-To: <20221111182535.64844-1-alex.bennee@linaro.org>
This removes the hacks to deal with empty current_cpu.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
v2
- update for new fields
- bool asserts
v3
- properly fail memory transactions from non-CPU sources
---
hw/timer/arm_mptimer.c | 49 +++++++++++++++++++++++++++++-------------
1 file changed, 34 insertions(+), 15 deletions(-)
diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c
index cdfca3000b..4618779ade 100644
--- a/hw/timer/arm_mptimer.c
+++ b/hw/timer/arm_mptimer.c
@@ -28,6 +28,7 @@
#include "migration/vmstate.h"
#include "qapi/error.h"
#include "qemu/module.h"
+#include "qemu/log.h"
#include "hw/core/cpu.h"
#define PTIMER_POLICY \
@@ -41,15 +42,23 @@
* which is used in both the ARM11MPCore and Cortex-A9MP.
*/
-static inline int get_current_cpu(ARMMPTimerState *s)
+static bool is_from_cpu(MemTxAttrs attrs)
{
- int cpu_id = current_cpu ? current_cpu->cpu_index : 0;
+ if (attrs.requester_type != MTRT_CPU) {
+ qemu_log_mask(LOG_UNIMP | LOG_GUEST_ERROR,
+ "%s: saw non-CPU transaction", __func__);
+ return false;
+ }
+ return true;
+}
+static int get_current_cpu(ARMMPTimerState *s, MemTxAttrs attrs)
+{
+ int cpu_id = attrs.requester_id;
if (cpu_id >= s->num_cpu) {
hw_error("arm_mptimer: num-cpu %d but this cpu is %d!\n",
s->num_cpu, cpu_id);
}
-
return cpu_id;
}
@@ -178,25 +187,35 @@ static void timerblock_write(void *opaque, hwaddr addr,
/* Wrapper functions to implement the "read timer/watchdog for
* the current CPU" memory regions.
*/
-static uint64_t arm_thistimer_read(void *opaque, hwaddr addr,
- unsigned size)
+static MemTxResult arm_thistimer_read(void *opaque, hwaddr addr, uint64_t *data,
+ unsigned size, MemTxAttrs attrs)
{
- ARMMPTimerState *s = (ARMMPTimerState *)opaque;
- int id = get_current_cpu(s);
- return timerblock_read(&s->timerblock[id], addr, size);
+ if (is_from_cpu(attrs)) {
+ ARMMPTimerState *s = (ARMMPTimerState *)opaque;
+ int id = get_current_cpu(s, attrs);
+ *data = timerblock_read(&s->timerblock[id], addr, size);
+ return MEMTX_OK;
+ } else {
+ return MEMTX_ACCESS_ERROR;
+ }
}
-static void arm_thistimer_write(void *opaque, hwaddr addr,
- uint64_t value, unsigned size)
+static MemTxResult arm_thistimer_write(void *opaque, hwaddr addr,
+ uint64_t value, unsigned size, MemTxAttrs attrs)
{
- ARMMPTimerState *s = (ARMMPTimerState *)opaque;
- int id = get_current_cpu(s);
- timerblock_write(&s->timerblock[id], addr, value, size);
+ if (is_from_cpu(attrs)) {
+ ARMMPTimerState *s = (ARMMPTimerState *)opaque;
+ int id = get_current_cpu(s, attrs);
+ timerblock_write(&s->timerblock[id], addr, value, size);
+ return MEMTX_OK;
+ } else {
+ return MEMTX_ACCESS_ERROR;
+ }
}
static const MemoryRegionOps arm_thistimer_ops = {
- .read = arm_thistimer_read,
- .write = arm_thistimer_write,
+ .read_with_attrs = arm_thistimer_read,
+ .write_with_attrs = arm_thistimer_write,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
--
2.34.1
next prev parent reply other threads:[~2022-11-11 18:27 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-11 18:25 [PATCH for 8.0 v5 00/20] use MemTxAttrs to avoid current_cpu in hw/ Alex Bennée
2022-11-11 18:25 ` [PATCH v5 01/20] hw: encode accessing CPU index in MemTxAttrs Alex Bennée
2022-11-12 4:18 ` Richard Henderson
2022-11-21 18:32 ` Peter Maydell
2022-11-11 18:25 ` [PATCH v5 02/20] target/arm: ensure TCG IO accesses set appropriate MemTxAttrs Alex Bennée
2022-11-12 5:17 ` Richard Henderson
2022-11-12 5:26 ` Richard Henderson
2022-11-11 18:25 ` [PATCH v5 03/20] target/arm: ensure HVF traps " Alex Bennée
2022-11-11 18:25 ` [PATCH v5 04/20] target/arm: ensure KVM " Alex Bennée
2022-11-12 5:29 ` Richard Henderson
2022-11-11 18:25 ` [PATCH v5 05/20] target/arm: ensure m-profile helpers " Alex Bennée
2022-11-12 5:26 ` Richard Henderson
2022-11-11 18:25 ` [PATCH v5 06/20] qtest: make read/write operation appear to be from CPU Alex Bennée
2022-11-11 18:25 ` [PATCH v5 07/20] hw/intc/gic: use MxTxAttrs to divine accessing CPU Alex Bennée
2022-11-11 18:25 ` Alex Bennée [this message]
2022-11-11 18:25 ` [PATCH v5 09/20] hw/arm: remove current_cpu hack from pxa2xx access Alex Bennée
2022-11-12 5:36 ` Richard Henderson
2022-11-13 19:43 ` Philippe Mathieu-Daudé
2022-11-11 18:25 ` [PATCH v5 10/20] target/microblaze: initialise MemTxAttrs for CPU access Alex Bennée
2022-11-11 19:41 ` Edgar E. Iglesias
2022-11-12 5:37 ` Richard Henderson
2022-11-13 19:44 ` Philippe Mathieu-Daudé
2022-11-11 18:25 ` [PATCH v5 11/20] target/sparc: " Alex Bennée
2022-11-12 1:02 ` Mark Cave-Ayland
2022-11-12 5:38 ` Richard Henderson
2022-11-13 19:45 ` Philippe Mathieu-Daudé
2022-11-11 18:25 ` [PATCH v5 12/20] target/riscv: " Alex Bennée
2022-11-11 18:25 ` [PATCH v5 13/20] target/i386: add explicit initialisation for MexTxAttrs Alex Bennée
2022-11-12 5:49 ` Richard Henderson
2022-11-11 18:25 ` [PATCH v5 14/20] hw/audio: explicitly set .requester_type for intel-hda Alex Bennée
2022-11-12 5:50 ` Richard Henderson
2022-11-13 19:50 ` Philippe Mathieu-Daudé
2022-11-21 18:39 ` Peter Maydell
2022-11-21 22:14 ` Philippe Mathieu-Daudé
2022-11-11 18:25 ` [PATCH v5 15/20] hw/i386: update vapic_write to use MemTxAttrs Alex Bennée
2022-11-12 5:51 ` Richard Henderson
2022-11-13 19:52 ` Philippe Mathieu-Daudé
2022-11-11 18:25 ` [PATCH v5 16/20] include: add MEMTXATTRS_MACHINE helper Alex Bennée
2022-11-12 5:52 ` Richard Henderson
2022-11-11 18:25 ` [PATCH v5 17/20] hw/intc: properly model IOAPIC MSI messages Alex Bennée
2022-11-12 5:57 ` Richard Henderson
2022-11-11 18:25 ` [PATCH v5 18/20] hw/i386: convert apic access to use MemTxAttrs Alex Bennée
2022-11-12 6:02 ` Richard Henderson
2022-11-21 18:43 ` Peter Maydell
2022-11-11 18:25 ` [PATCH v5 19/20] hw/isa: derive CPUState from MemTxAttrs in apm_ioport_writeb Alex Bennée
2022-11-12 6:04 ` Richard Henderson
2022-11-13 20:04 ` Philippe Mathieu-Daudé
2022-11-11 18:25 ` [PATCH v5 20/20] include/hw: add commentary to current_cpu export Alex Bennée
2022-11-12 6:05 ` Richard Henderson
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