[PATCH for 7.2? v2 0/2] Arm GICv2 fixes

[PATCH for 7.2? v2 0/2] Arm GICv2 fixes

[Alex Bennée]

Hi Peter,

These are the 2 GICv2 patches as you suggested in the last review -
this time with an updated commit message for the second patch. I don't
know if they qualify for 7.2 but here they are if you want them.

Alex Bennée (2):
  hw/intc: clean-up access to GIC multi-byte registers
  hw/intc: add implementation of GICD_IIDR to Arm GIC

 hw/intc/arm_gic.c | 28 +++++++++++++++++++++-------
 1 file changed, 21 insertions(+), 7 deletions(-)

-- 
2.34.1

[PATCH v2 1/2] hw/intc: clean-up access to GIC multi-byte registers

[Alex Bennée]

gic_dist_readb was returning a word value which just happened to work
as a result of the way we OR the data together. Lets fix it so only
the explicit byte is returned for each part of GICD_TYPER. I've
changed the return type to uint8_t although the overflow is only
detected with an explicit -Wconversion.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/intc/arm_gic.c | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 492b2421ab..1a04144c38 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -941,7 +941,7 @@ static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
     gic_update(s);
 }
 
-static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
+static uint8_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
 {
     GICState *s = (GICState *)opaque;
     uint32_t res;
@@ -955,6 +955,7 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
     cm = 1 << cpu;
     if (offset < 0x100) {
         if (offset == 0) {      /* GICD_CTLR */
+            /* We rely here on the only non-zero bits being in byte 0 */
             if (s->security_extn && !attrs.secure) {
                 /* The NS bank of this register is just an alias of the
                  * EnableGrp1 bit in the S bank version.
@@ -964,11 +965,14 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
                 return s->ctlr;
             }
         }
-        if (offset == 4)
-            /* Interrupt Controller Type Register */
-            return ((s->num_irq / 32) - 1)
-                    | ((s->num_cpu - 1) << 5)
-                    | (s->security_extn << 10);
+        if (offset == 4) {
+            /* GICD_TYPER byte 0 */
+            return ((s->num_irq / 32) - 1) | ((s->num_cpu - 1) << 5);
+        }
+        if (offset == 5) {
+            /* GICD_TYPER byte 1 */
+            return (s->security_extn << 2);
+        }
         if (offset < 0x08)
             return 0;
         if (offset >= 0x80) {
-- 
2.34.1

[PATCH v2 2/2] hw/intc: add implementation of GICD_IIDR to Arm GIC

[Alex Bennée]

a66a24585f (hw/intc/arm_gic: Implement read of GICC_IIDR) implemented
this for the CPU interface register. The fact we don't implement it
shows up when running Xen with -d guest_error which is definitely
wrong because the guest is perfectly entitled to read it.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

---
v2
  - checkpatch fixes.
v3
  - re-base on re-flow with if
v4
  - fix the commit message
---
 hw/intc/arm_gic.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 1a04144c38..7a34bc0998 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -973,8 +973,18 @@ static uint8_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
             /* GICD_TYPER byte 1 */
             return (s->security_extn << 2);
         }
-        if (offset < 0x08)
+        if (offset == 8) {
+            /* GICD_IIDR byte 0 */
+            return 0x3b; /* Arm JEP106 identity */
+        }
+        if (offset == 9) {
+            /* GICD_IIDR byte 1 */
+            return 0x04; /* Arm JEP106 identity */
+        }
+        if (offset < 0x0c) {
+            /* All other bytes in this range are RAZ */
             return 0;
+        }
         if (offset >= 0x80) {
             /* Interrupt Group Registers: these RAZ/WI if this is an NS
              * access to a GIC with the security extensions, or if the GIC
-- 
2.34.1

Re: [PATCH v2 2/2] hw/intc: add implementation of GICD_IIDR to Arm GIC

[Philippe Mathieu-Daudé]

On 15/11/22 17:17, Alex Bennée wrote:
> a66a24585f (hw/intc/arm_gic: Implement read of GICC_IIDR) implemented
> this for the CPU interface register. The fact we don't implement it
> shows up when running Xen with -d guest_error which is definitely
> wrong because the guest is perfectly entitled to read it.
> 
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
> 
> ---
> v2
>    - checkpatch fixes.
> v3
>    - re-base on re-flow with if
> v4
>    - fix the commit message
> ---
>   hw/intc/arm_gic.c | 12 +++++++++++-
>   1 file changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
> index 1a04144c38..7a34bc0998 100644
> --- a/hw/intc/arm_gic.c
> +++ b/hw/intc/arm_gic.c
> @@ -973,8 +973,18 @@ static uint8_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
>               /* GICD_TYPER byte 1 */
>               return (s->security_extn << 2);
>           }
> -        if (offset < 0x08)
> +        if (offset == 8) {
> +            /* GICD_IIDR byte 0 */
> +            return 0x3b; /* Arm JEP106 identity */
> +        }
> +        if (offset == 9) {
> +            /* GICD_IIDR byte 1 */
> +            return 0x04; /* Arm JEP106 identity */

Possible future cleanup, define JEP106_ID_ARM:

$ git grep 0x43b
hw/intc/arm_gic.c:1671:            *data = (s->revision << 16) | 0x43b;
hw/intc/gicv3_internal.h:743:    return 0x43b;
hw/misc/armv7m_ras.c:26:        *data = 0x43b;

> +        }
> +        if (offset < 0x0c) {
> +            /* All other bytes in this range are RAZ */
>               return 0;
> +        }

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Re: [PATCH v2 2/2] hw/intc: add implementation of GICD_IIDR to Arm GIC

[Peter Maydell]

On Tue, 15 Nov 2022 at 16:29, Philippe Mathieu-Daudé <philmd@linaro.org> wrote:
> Possible future cleanup, define JEP106_ID_ARM:
>
> $ git grep 0x43b
> hw/intc/arm_gic.c:1671:            *data = (s->revision << 16) | 0x43b;
> hw/intc/gicv3_internal.h:743:    return 0x43b;
> hw/misc/armv7m_ras.c:26:        *data = 0x43b;

I think that's probably not worthwhile, because the datasheet gives
you the hex value of the ID register for the device, and if we
hide that behind a #define then now to check that the value is
right you need to go look at the #define line.

Put another way, the important thing is "this register holds the
value 0x43b", and it's just a point of information that that happens
to correspond to a JEP-106 manufacturer ID code value.

thanks
-- PMM

Re: [PATCH for 7.2? v2 0/2] Arm GICv2 fixes

[Peter Maydell]

On Tue, 15 Nov 2022 at 16:17, Alex Bennée <alex.bennee@linaro.org> wrote:
>
> Hi Peter,
>
> These are the 2 GICv2 patches as you suggested in the last review -
> this time with an updated commit message for the second patch. I don't
> know if they qualify for 7.2 but here they are if you want them.
>
> Alex Bennée (2):
>   hw/intc: clean-up access to GIC multi-byte registers
>   hw/intc: add implementation of GICD_IIDR to Arm GIC


Applied to target-arm.next, thanks.

-- PMM