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[77.13.67.205]) by smtp.gmail.com with ESMTPSA id u10-20020a1709061daa00b007b2a3cad2cfsm4026785ejh.132.2022.11.20.07.06.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Nov 2022 07:06:31 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: John G Johnson , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang , Aurelien Jarno , Paolo Bonzini , Marcel Apfelbaum , "Michael S. Tsirkin" , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Elena Ufimtseva , Eduardo Habkost , Jagannathan Raman , Richard Henderson , qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Bernhard Beschow Subject: [PATCH v2 0/3] Decouple INTx-to-LNKx routing from south bridges Date: Sun, 20 Nov 2022 16:05:47 +0100 Message-Id: <20221120150550.63059-1-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=shentey@gmail.com; helo=mail-ed1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org v1:=0D =3D=3D=3D=0D =0D During my PIIX consolidation work [1] I've noticed that both PIIX models ha= ve=0D quite different pci_slot_get_pirq() implementations. These functions seem t= o=0D map PCI INTx pins to input pins of a programmable interrupt router which is= =0D AFAIU board-specific. IOW, board-specific assumptions are baked into the de= vice=0D models which prevent e.g. the whole PIIX4 south bridge to be reusable in th= e PC=0D machine.=0D =0D This series first factors out pci_bus_map_irqs() from pci_bus_irqs() which= =0D then allowes for moving the two board-specific PIIX pci_slot_get_pirq()=0D funtions into their respective boards. With these changes, the PIIX4 south= =0D bridge could eventually become an alternative to the PIIX3-Frankenstein=0D solution in the PC machine.=0D =0D v2:=0D =3D=3D=3D=0D * Remove RFC tag from whole series=0D * New patch to split pci_bus_irqs()=0D * Remove VT82xx patch which was just a demonstration=0D =0D Testing done:=0D * `make check`=0D * `make check-avocado`=0D * `qemu-system-mips64el -M malta -kernel vmlinux-3.2.0-4-5kc-malta -hda deb= ian_wheezy_mipsel_standard.qcow2 -append "root=3D/dev/sda1 console=3DttyS0"= `=0D * `qemu-system-x86_64 -M pc -m 2G -cdrom manjaro-kde-21.3.2-220704-linux515= .iso`=0D =0D Thanks,=0D Bernhard=0D =0D [1] https://lists.nongnu.org/archive/html/qemu-devel/2022-10/msg03941.html= =0D =0D Bernhard Beschow (3):=0D hw/pci/pci: Factor out pci_bus_map_irqs() from pci_bus_irqs()=0D hw/isa/piix3: Decouple INTx-to-LNKx routing which is board-specific=0D hw/isa/piix4: Decouple INTx-to-LNKx routing which is board-specific=0D =0D hw/i386/pc_piix.c | 16 ++++++++++++++++=0D hw/i386/pc_q35.c | 4 ++--=0D hw/isa/piix3.c | 17 ++---------------=0D hw/isa/piix4.c | 27 +--------------------------=0D hw/mips/malta.c | 28 ++++++++++++++++++++++++++++=0D hw/pci-host/raven.c | 3 ++-=0D hw/pci-host/versatile.c | 3 ++-=0D hw/pci/pci.c | 12 +++++++++---=0D hw/remote/machine.c | 3 ++-=0D include/hw/pci/pci.h | 3 ++-=0D 10 files changed, 66 insertions(+), 50 deletions(-)=0D =0D -- =0D 2.38.1=0D =0D