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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id t1-20020a1c7701000000b003cf4d99fd2asm13296725wmi.6.2022.11.21.05.02.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Nov 2022 05:02:40 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 0/5] target-arm queue Date: Mon, 21 Nov 2022 13:02:34 +0000 Message-Id: <20221121130239.1138631-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi; here's a collection of Arm bug fixes for rc2. thanks -- PMM The following changes since commit a082fab9d259473a9d5d53307cf83b1223301181: Merge tag 'pull-ppc-20221117' of https://gitlab.com/danielhb/qemu into staging (2022-11-17 12:39:38 -0500) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20221121 for you to fetch changes up to 312b71abce3005ca7294dc0db7d548dc7cc41fbf: target/arm: Limit LPA2 effective output address when TCR.DS == 0 (2022-11-21 11:46:46 +0000) ---------------------------------------------------------------- target-arm queue: * hw/sd: Fix sun4i allwinner-sdhost for U-Boot * hw/intc: add implementation of GICD_IIDR to Arm GIC * tests/avocado/boot_linux.py: Bump aarch64 virt test timeout * target/arm: Limit LPA2 effective output address when TCR.DS == 0 ---------------------------------------------------------------- Alex Bennée (2): hw/intc: clean-up access to GIC multi-byte registers hw/intc: add implementation of GICD_IIDR to Arm GIC Ard Biesheuvel (1): target/arm: Limit LPA2 effective output address when TCR.DS == 0 Peter Maydell (1): tests/avocado/boot_linux.py: Bump aarch64 virt test timeout to 720s Strahinja Jankovic (1): hw/sd: Fix sun4i allwinner-sdhost for U-Boot include/hw/sd/allwinner-sdhost.h | 1 + hw/intc/arm_gic.c | 28 ++++++++++++----- hw/sd/allwinner-sdhost.c | 67 +++++++++++++++++++++++++++------------- target/arm/ptw.c | 8 +++++ tests/avocado/boot_linux.py | 2 +- 5 files changed, 77 insertions(+), 29 deletions(-)