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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Igor Mammedov , Volker =?utf-8?Q?R=C3=BCmelin?= , Marcel Apfelbaum Subject: [PULL 3/8] acpi: x86: move RPQx field back to _SB scope Message-ID: <20221122102227.6603-4-mst@redhat.com> References: <20221122102227.6603-1-mst@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20221122102227.6603-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Igor Mammedov Commit 47a373faa6b2 (acpi: pc/q35: drop ad-hoc PCI-ISA bridge AML routines and let bus ennumeration generate AML) moved ISA bridge AML generation to respective devices and was using aml_alias() to provide PRQx fields in _SB. scope. However, it turned out that SeaBIOS was not able to process Alias opcode when parsing DSDT, resulting in lack of keyboard during boot (SeaBIOS console, grub, FreeDOS). While fix for SeaBIOS is posted https://mail.coreboot.org/hyperkitty/list/seabios@seabios.org/thread/RGPL7HESH5U5JRLEO6FP77CZVHZK5J65/ fixed SeaBIOS might not make into QEMU-7.2 in time. Hence this workaround that puts PRQx back into _SB scope and gets rid of aliases in ISA bridge description, so DSDT will be parsable by broken SeaBIOS. That brings back hardcoded references to ISA bridge PCI0.S08.P40C/PCI0.SF8.PIRQ where middle part now is auto generated based on slot it's plugged in, but it should be fine as bridge initialization also hardcodes PCI address of the bridge so it can't ever move. Once QEMU tree has fixed SeaBIOS blob, we should be able to drop this part and revert back to alias based approach Reported-by: Volker Rümelin Signed-off-by: Igor Mammedov Message-Id: <20221121153613.3972225-3-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/isa/lpc_ich9.c | 16 ++++------------ hw/isa/piix3.c | 12 ++++-------- 2 files changed, 8 insertions(+), 20 deletions(-) diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index 0b0a83e080..6c44cc9767 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -813,12 +813,13 @@ static void build_ich9_isa_aml(AcpiDevAmlIf *adev, Aml *scope) BusChild *kid; ICH9LPCState *s = ICH9_LPC_DEVICE(adev); BusState *bus = BUS(s->isa_bus); + Aml *sb_scope = aml_scope("\\_SB"); /* ICH9 PCI to ISA irq remapping */ aml_append(scope, aml_operation_region("PIRQ", AML_PCI_CONFIG, aml_int(0x60), 0x0C)); /* Fields declarion has to happen *after* operation region */ - field = aml_field("PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); + field = aml_field("PCI0.SF8.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); aml_append(field, aml_named_field("PRQA", 8)); aml_append(field, aml_named_field("PRQB", 8)); aml_append(field, aml_named_field("PRQC", 8)); @@ -828,17 +829,8 @@ static void build_ich9_isa_aml(AcpiDevAmlIf *adev, Aml *scope) aml_append(field, aml_named_field("PRQF", 8)); aml_append(field, aml_named_field("PRQG", 8)); aml_append(field, aml_named_field("PRQH", 8)); - aml_append(scope, field); - - /* hack: put fields into _SB scope for LNKx to find them */ - aml_append(scope, aml_alias("PRQA", "\\_SB.PRQA")); - aml_append(scope, aml_alias("PRQB", "\\_SB.PRQB")); - aml_append(scope, aml_alias("PRQC", "\\_SB.PRQC")); - aml_append(scope, aml_alias("PRQD", "\\_SB.PRQD")); - aml_append(scope, aml_alias("PRQE", "\\_SB.PRQE")); - aml_append(scope, aml_alias("PRQF", "\\_SB.PRQF")); - aml_append(scope, aml_alias("PRQG", "\\_SB.PRQG")); - aml_append(scope, aml_alias("PRQH", "\\_SB.PRQH")); + aml_append(sb_scope, field); + aml_append(scope, sb_scope); QTAILQ_FOREACH(kid, &bus->children, sibling) { call_dev_aml_func(DEVICE(kid->child), scope); diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index f9b4af5c05..eabad7ba58 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -318,24 +318,20 @@ static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) { Aml *field; BusChild *kid; + Aml *sb_scope = aml_scope("\\_SB"); BusState *bus = qdev_get_child_bus(DEVICE(adev), "isa.0"); /* PIIX PCI to ISA irq remapping */ aml_append(scope, aml_operation_region("P40C", AML_PCI_CONFIG, aml_int(0x60), 0x04)); /* Fields declarion has to happen *after* operation region */ - field = aml_field("P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); + field = aml_field("PCI0.S08.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); aml_append(field, aml_named_field("PRQ0", 8)); aml_append(field, aml_named_field("PRQ1", 8)); aml_append(field, aml_named_field("PRQ2", 8)); aml_append(field, aml_named_field("PRQ3", 8)); - aml_append(scope, field); - - /* hack: put fields into _SB scope for LNKx to find them */ - aml_append(scope, aml_alias("PRQ0", "\\_SB.PRQ0")); - aml_append(scope, aml_alias("PRQ1", "\\_SB.PRQ1")); - aml_append(scope, aml_alias("PRQ2", "\\_SB.PRQ2")); - aml_append(scope, aml_alias("PRQ3", "\\_SB.PRQ3")); + aml_append(sb_scope, field); + aml_append(scope, sb_scope); QTAILQ_FOREACH(kid, &bus->children, sibling) { call_dev_aml_func(DEVICE(kid->child), scope); -- MST