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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u17-20020a05600c19d100b003c6f8d30e40sm9728258wmq.31.2022.11.25.03.52.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Nov 2022 03:52:46 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Gerd Hoffmann , "Michael S. Tsirkin" , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Greg Kurz , Marcel Apfelbaum , qemu-ppc@nongnu.org Subject: [PATCH for-8.0 5/7] hw/intc/xics: Reset TYPE_ICS objects with device_cold_reset() Date: Fri, 25 Nov 2022 11:52:38 +0000 Message-Id: <20221125115240.3005559-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221125115240.3005559-1-peter.maydell@linaro.org> References: <20221125115240.3005559-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The realize method for the TYPE_ICS class uses qemu_register_reset() to register a reset handler, as a workaround for the fact that currently objects which directly inherit from TYPE_DEVICE don't get automatically reset. However, the reset function directly calls ics_reset(), which is the function that implements the legacy reset method. This means that only the parent class's data gets reset, and a subclass which also needs to handle reset, like TYPE_PHB3_MSI, has to register its own reset function. Make the TYPE_ICS reset function call device_cold_reset() instead: this will handle reset for both the parent class and the subclass, and will work whether the classes are using legacy reset or 3-phase reset. This allows us to remove the reset function that the subclass currently has to set up. Signed-off-by: Peter Maydell --- hw/intc/xics.c | 2 +- hw/pci-host/pnv_phb3_msi.c | 7 ------- 2 files changed, 1 insertion(+), 8 deletions(-) diff --git a/hw/intc/xics.c b/hw/intc/xics.c index dcd021af668..dd130467ccc 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -593,7 +593,7 @@ static void ics_reset(DeviceState *dev) static void ics_reset_handler(void *dev) { - ics_reset(dev); + device_cold_reset(dev); } static void ics_realize(DeviceState *dev, Error **errp) diff --git a/hw/pci-host/pnv_phb3_msi.c b/hw/pci-host/pnv_phb3_msi.c index 2f4112907b8..ae908fd9e41 100644 --- a/hw/pci-host/pnv_phb3_msi.c +++ b/hw/pci-host/pnv_phb3_msi.c @@ -239,11 +239,6 @@ static void phb3_msi_reset(DeviceState *dev) msi->rba_sum = 0; } -static void phb3_msi_reset_handler(void *dev) -{ - phb3_msi_reset(dev); -} - void pnv_phb3_msi_update_config(Phb3MsiState *msi, uint32_t base, uint32_t count) { @@ -272,8 +267,6 @@ static void phb3_msi_realize(DeviceState *dev, Error **errp) } msi->qirqs = qemu_allocate_irqs(phb3_msi_set_irq, msi, ics->nr_irqs); - - qemu_register_reset(phb3_msi_reset_handler, dev); } static void phb3_msi_instance_init(Object *obj) -- 2.25.1