[PATCH v5 0/7] Add ARM Cortex-R52 CPU

[<tobias.roehmel@rwth-aachen.de>]

From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>

No worries about the delay. I'm glad you are looking at it :)

v5:
1. Adjusted the spacing as requested
2. Removed cp 15
3. Rebased and put assert back
4. Fixed indention issues
5.
- Made hprbar etc pointers instead of arrays
- Fixed the logic/bound issues
- For the VMSTATE change I looked at pmsav7.drbar which
  is a pointer and is handled as an array. I assume
  this works for hprbar/hprlar
6.
- In pmsav7_use_background_region there are 2 cases were we don't
  want to look at the SCTLR_BR bit (c1.3 in manual supplement):
  - The respective MPU is enabled and
    - We are in the second translation stage
    - We are in EL0
  I think the code does that now and doesn't influence any other
  code. I put the V8 check in there because the function is also
  called from get_phys_addr_pmsav7
- I put the fi->level behaviour back the way it was
- Fixed UWXN/WXN

Tobias Röhmel (7):
  target/arm: Don't add all MIDR aliases for cores that implement PMSA
  target/arm: Make RVBAR available for all ARMv8 CPUs
  target/arm: Make stage_2_format for cache attributes optional
  target/arm: Enable TTBCR_EAE for ARMv8-R AArch32
  target/arm: Add PMSAv8r registers
  target/arm: Add PMSAv8r functionality
  target/arm: Add ARM Cortex-R52 CPU

 target/arm/cpu.c          |  30 +++-
 target/arm/cpu.h          |   6 +
 target/arm/cpu_tcg.c      |  42 +++++
 target/arm/debug_helper.c |   3 +
 target/arm/helper.c       | 333 ++++++++++++++++++++++++++++++++++++--
 target/arm/internals.h    |   4 +
 target/arm/machine.c      |  28 ++++
 target/arm/ptw.c          | 137 +++++++++++++---
 target/arm/tlb_helper.c   |   4 +
 9 files changed, 550 insertions(+), 37 deletions(-)

-- 
2.34.1