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charset=us-ascii Content-Disposition: inline In-Reply-To: X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: ynZ0cYOexTpdRnRvhCk7a9RawgwjOgG- X-Proofpoint-GUID: ynZ0cYOexTpdRnRvhCk7a9RawgwjOgG- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-11-29_01,2022-11-28_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 impostorscore=0 phishscore=0 suspectscore=0 malwarescore=0 mlxlogscore=836 mlxscore=0 adultscore=0 spamscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2211290009 Received-SPF: pass client-ip=148.163.156.1; envelope-from=iii@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Sat, Nov 05, 2022 at 09:27:07AM +1100, Richard Henderson wrote: > On 11/4/22 00:42, Ilya Leoshkevich wrote: > > On Wed, Oct 05, 2022 at 08:44:07PM -0700, Richard Henderson wrote: > > > Masking after the fact in s390x_tr_init_disas_context > > > provides incorrect information to tb_lookup. > > > > > > Signed-off-by: Richard Henderson > > > --- > > > target/s390x/cpu.h | 13 +++++++------ > > > target/s390x/tcg/translate.c | 6 ------ > > > 2 files changed, 7 insertions(+), 12 deletions(-) > > > > How can we end up in a situation where this matters? E.g. if we are in > > 64-bit mode and execute > > > > 0xa12345678: sam31 > > > > we will get a specification exception, and cpu_get_tb_cpu_state() will > > not run. And for valid 31-bit addresses masking should be a no-op. > > Ah, true. I was mislead by the presence of the code in > s390x_tr_init_disas_context. Perhaps a tcg_debug_assert or just a comment? An assert sounds good to me. I tried the following diff with the attached test and it worked: --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -390,7 +390,12 @@ static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc, } *pflags = flags; *cs_base = env->ex_value; - *pc = (flags & FLAG_MASK_64 ? env->psw.addr : env->psw.addr & 0x7fffffff); + if (!(flags & FLAG_MASK_32)) { + g_assert(env->psw.addr <= 0xffffff); + } else if (!(flags & FLAG_MASK_64)) { + g_assert(env->psw.addr <= 0x7fffffff); + } + *pc = env->psw.addr; } /* PER bits from control register 9 */ diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 24dc57a8816..a50453dd0d4 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -6464,6 +6464,12 @@ static void s390x_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc = container_of(dcbase, DisasContext, base); + if (!(dc->base.tb->flags & FLAG_MASK_32)) { + tcg_debug_assert(dc->base.pc_first <= 0xffffff); + } else if (!(dc->base.tb->flags & FLAG_MASK_64)) { + tcg_debug_assert(dc->base.pc_first <= 0x7fffffff); + } + dc->pc_save = dc->base.pc_first; dc->cc_op = CC_OP_DYNAMIC; dc->ex_value = dc->base.tb->cs_base;