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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Wilfred Mallawa" <wilfred.mallawa@wdc.com>
Subject: [PATCH v3 03/34] tcg/s390x: Fix coding style
Date: Thu,  1 Dec 2022 21:39:27 -0800	[thread overview]
Message-ID: <20221202053958.223890-4-richard.henderson@linaro.org> (raw)
In-Reply-To: <20221202053958.223890-1-richard.henderson@linaro.org>

From: Philippe Mathieu-Daudé <philmd@linaro.org>

We are going to modify this code, so fix its style first to avoid:

  ERROR: spaces required around that '*' (ctx:VxV)
  #281: FILE: tcg/s390x/tcg-target.c.inc:1224:
  +        uintptr_t mask = ~(0xffffull << i*16);
                                            ^

Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221130132654.76369-2-philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/s390x/tcg-target.c.inc | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index 33becd7694..f1d3907cd8 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -802,9 +802,9 @@ static bool maybe_out_small_movi(TCGContext *s, TCGType type,
     }
 
     for (i = 0; i < 4; i++) {
-        tcg_target_long mask = 0xffffull << i*16;
+        tcg_target_long mask = 0xffffull << i * 16;
         if ((uval & mask) == uval) {
-            tcg_out_insn_RI(s, lli_insns[i], ret, uval >> i*16);
+            tcg_out_insn_RI(s, lli_insns[i], ret, uval >> i * 16);
             return true;
         }
     }
@@ -1221,9 +1221,9 @@ static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)
 
     /* Try all 32-bit insns that can perform it in one go.  */
     for (i = 0; i < 4; i++) {
-        tcg_target_ulong mask = ~(0xffffull << i*16);
+        tcg_target_ulong mask = ~(0xffffull << i * 16);
         if (((val | ~valid) & mask) == mask) {
-            tcg_out_insn_RI(s, ni_insns[i], dest, val >> i*16);
+            tcg_out_insn_RI(s, ni_insns[i], dest, val >> i * 16);
             return;
         }
     }
@@ -1231,9 +1231,9 @@ static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)
     /* Try all 48-bit insns that can perform it in one go.  */
     if (HAVE_FACILITY(EXT_IMM)) {
         for (i = 0; i < 2; i++) {
-            tcg_target_ulong mask = ~(0xffffffffull << i*32);
+            tcg_target_ulong mask = ~(0xffffffffull << i * 32);
             if (((val | ~valid) & mask) == mask) {
-                tcg_out_insn_RIL(s, nif_insns[i], dest, val >> i*32);
+                tcg_out_insn_RIL(s, nif_insns[i], dest, val >> i * 32);
                 return;
             }
         }
@@ -1279,9 +1279,9 @@ static void tgen_ori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)
 
     /* Try all 32-bit insns that can perform it in one go.  */
     for (i = 0; i < 4; i++) {
-        tcg_target_ulong mask = (0xffffull << i*16);
+        tcg_target_ulong mask = (0xffffull << i * 16);
         if ((val & mask) != 0 && (val & ~mask) == 0) {
-            tcg_out_insn_RI(s, oi_insns[i], dest, val >> i*16);
+            tcg_out_insn_RI(s, oi_insns[i], dest, val >> i * 16);
             return;
         }
     }
@@ -1289,9 +1289,9 @@ static void tgen_ori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)
     /* Try all 48-bit insns that can perform it in one go.  */
     if (HAVE_FACILITY(EXT_IMM)) {
         for (i = 0; i < 2; i++) {
-            tcg_target_ulong mask = (0xffffffffull << i*32);
+            tcg_target_ulong mask = (0xffffffffull << i * 32);
             if ((val & mask) != 0 && (val & ~mask) == 0) {
-                tcg_out_insn_RIL(s, oif_insns[i], dest, val >> i*32);
+                tcg_out_insn_RIL(s, oif_insns[i], dest, val >> i * 32);
                 return;
             }
         }
-- 
2.34.1



  parent reply	other threads:[~2022-12-02  5:44 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-02  5:39 [PATCH for-8.0 v3 00/34] tcg misc patches Richard Henderson
2022-12-02  5:39 ` [PATCH v3 01/34] tcg: convert tcg/README to rst Richard Henderson
2022-12-02  5:39 ` [PATCH v3 02/34] meson: Move CONFIG_TCG_INTERPRETER to config_host Richard Henderson
2022-12-02  9:42   ` Paolo Bonzini
2022-12-02  5:39 ` Richard Henderson [this message]
2022-12-02  5:39 ` [PATCH v3 04/34] tcg: Cleanup trailing whitespace Richard Henderson
2022-12-02  7:33   ` Philippe Mathieu-Daudé
2022-12-02  5:39 ` [PATCH v3 05/34] tcg: Fix tcg_reg_alloc_dup* Richard Henderson
2022-12-02  5:39 ` [PATCH v3 06/34] tcg: Centralize updates to reg_to_temp Richard Henderson
2022-12-02  5:39 ` [PATCH v3 07/34] tcg: Remove check_regs Richard Henderson
2022-12-02  5:39 ` [PATCH v3 08/34] tcg: Tidy tcg_reg_alloc_op Richard Henderson
2022-12-02  5:39 ` [PATCH v3 09/34] tcg: Introduce paired register allocation Richard Henderson
2022-12-02  5:39 ` [PATCH v3 10/34] tcg: Remove TCG_TARGET_STACK_GROWSUP Richard Henderson
2022-12-02  5:39 ` [PATCH v3 11/34] accel/tcg: Set cflags_next_tb in cpu_common_initfn Richard Henderson
2022-12-02  5:39 ` [PATCH v3 12/34] target/sparc: Avoid TCGV_{LOW,HIGH} Richard Henderson
2022-12-02  5:39 ` [PATCH v3 13/34] tcg: Move TCG_{LOW,HIGH} to tcg-internal.h Richard Henderson
2022-12-02  5:39 ` [PATCH v3 14/34] tcg: Add temp_subindex to TCGTemp Richard Henderson
2022-12-02  5:39 ` [PATCH v3 15/34] tcg: Simplify calls to temp_sync vs mem_coherent Richard Henderson
2022-12-02  5:39 ` [PATCH v3 16/34] tcg: Allocate TCGTemp pairs in host memory order Richard Henderson
2022-12-02  5:39 ` [PATCH v3 17/34] tcg: Move TCG_TYPE_COUNT outside enum Richard Henderson
2022-12-02  5:39 ` [PATCH v3 18/34] tcg: Introduce tcg_type_size Richard Henderson
2022-12-02  5:39 ` [PATCH v3 19/34] tcg: Introduce TCGCallReturnKind and TCGCallArgumentKind Richard Henderson
2022-12-02  5:39 ` [PATCH v3 20/34] tcg: Replace TCG_TARGET_CALL_ALIGN_ARGS with TCG_TARGET_CALL_ARG_I64 Richard Henderson
2022-12-02  5:39 ` [PATCH v3 21/34] tcg: Replace TCG_TARGET_EXTEND_ARGS with TCG_TARGET_CALL_ARG_I32 Richard Henderson
2022-12-02  5:39 ` [PATCH v3 22/34] tcg: Use TCG_CALL_ARG_EVEN for TCI special case Richard Henderson
2022-12-02  5:39 ` [PATCH v3 23/34] accel/tcg/plugin: Don't search for the function pointer index Richard Henderson
2022-12-02  5:39 ` [PATCH v3 24/34] accel/tcg/plugin: Avoid duplicate copy in copy_call Richard Henderson
2022-12-02  5:39 ` [PATCH v3 25/34] accel/tcg/plugin: Use copy_op in append_{udata, mem}_cb Richard Henderson
2022-12-02  5:39 ` [PATCH v3 26/34] tci: MAX_OPC_PARAM_IARGS is no longer used Richard Henderson
2022-12-02  5:39 ` [PATCH v3 27/34] tcg: Vary the allocation size for TCGOp Richard Henderson
2022-12-02  5:39 ` [PATCH v3 28/34] tcg: Use output_pref wrapper function Richard Henderson
2022-12-02  5:39 ` [PATCH v3 29/34] tcg: Reorg function calls Richard Henderson
2022-12-06 15:28   ` Ilya Leoshkevich
2022-12-06 15:49     ` Richard Henderson
2022-12-06 15:58       ` Ilya Leoshkevich
2022-12-02  5:39 ` [PATCH v3 30/34] tcg: Convert typecode_to_ffi from array to function Richard Henderson
2022-12-02  5:39 ` [PATCH v3 31/34] tcg: Factor init_ffi_layouts() out of tcg_context_init() Richard Henderson
2022-12-02  5:39 ` [PATCH v3 32/34] tcg: Move ffi_cif pointer into TCGHelperInfo Richard Henderson
2022-12-02  5:39 ` [PATCH v3 33/34] tcg/aarch64: Merge tcg_out_callr into tcg_out_call Richard Henderson
2022-12-02  5:39 ` [PATCH v3 34/34] tcg: Add TCGHelperInfo argument to tcg_out_call Richard Henderson

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