From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: thuth@redhat.com, iii@linux.ibm.com
Subject: [PATCH v3 05/13] tcg/s390x: Distinguish RIE formats
Date: Thu, 1 Dec 2022 22:51:52 -0800 [thread overview]
Message-ID: <20221202065200.224537-6-richard.henderson@linaro.org> (raw)
In-Reply-To: <20221202065200.224537-1-richard.henderson@linaro.org>
There are multiple variations, with different fields.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/s390x/tcg-target.c.inc | 47 +++++++++++++++++++++-----------------
1 file changed, 26 insertions(+), 21 deletions(-)
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index a489b3359e..d02b433271 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -133,16 +133,19 @@ typedef enum S390Opcode {
RI_OILL = 0xa50b,
RI_TMLL = 0xa701,
- RIE_CGIJ = 0xec7c,
- RIE_CGRJ = 0xec64,
- RIE_CIJ = 0xec7e,
- RIE_CLGRJ = 0xec65,
- RIE_CLIJ = 0xec7f,
- RIE_CLGIJ = 0xec7d,
- RIE_CLRJ = 0xec77,
- RIE_CRJ = 0xec76,
- RIE_LOCGHI = 0xec46,
- RIE_RISBG = 0xec55,
+ RIEb_CGRJ = 0xec64,
+ RIEb_CLGRJ = 0xec65,
+ RIEb_CLRJ = 0xec77,
+ RIEb_CRJ = 0xec76,
+
+ RIEc_CGIJ = 0xec7c,
+ RIEc_CIJ = 0xec7e,
+ RIEc_CLGIJ = 0xec7d,
+ RIEc_CLIJ = 0xec7f,
+
+ RIEf_RISBG = 0xec55,
+
+ RIEg_LOCGHI = 0xec46,
RRE_AGR = 0xb908,
RRE_ALGR = 0xb90a,
@@ -561,7 +564,7 @@ static void tcg_out_insn_RI(TCGContext *s, S390Opcode op, TCGReg r1, int i2)
tcg_out32(s, (op << 16) | (r1 << 20) | (i2 & 0xffff));
}
-static void tcg_out_insn_RIE(TCGContext *s, S390Opcode op, TCGReg r1,
+static void tcg_out_insn_RIEg(TCGContext *s, S390Opcode op, TCGReg r1,
int i2, int m3)
{
tcg_out16(s, (op & 0xff00) | (r1 << 4) | m3);
@@ -1008,9 +1011,9 @@ static inline void tcg_out_risbg(TCGContext *s, TCGReg dest, TCGReg src,
int msb, int lsb, int ofs, int z)
{
/* Format RIE-f */
- tcg_out16(s, (RIE_RISBG & 0xff00) | (dest << 4) | src);
+ tcg_out16(s, (RIEf_RISBG & 0xff00) | (dest << 4) | src);
tcg_out16(s, (msb << 8) | (z << 7) | lsb);
- tcg_out16(s, (ofs << 8) | (RIE_RISBG & 0xff));
+ tcg_out16(s, (ofs << 8) | (RIEf_RISBG & 0xff));
}
static void tgen_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
@@ -1350,7 +1353,7 @@ static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond,
/* Emit: d = 0, d = (cc ? 1 : d). */
cc = tgen_cmp(s, type, cond, c1, c2, c2const, false);
tcg_out_movi(s, TCG_TYPE_I64, dest, 0);
- tcg_out_insn(s, RIE, LOCGHI, dest, 1, cc);
+ tcg_out_insn(s, RIEg, LOCGHI, dest, 1, cc);
return;
}
@@ -1443,7 +1446,7 @@ static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg dest,
if (HAVE_FACILITY(LOAD_ON_COND)) {
cc = tgen_cmp(s, type, c, c1, c2, c2const, false);
if (v3const) {
- tcg_out_insn(s, RIE, LOCGHI, dest, v3, cc);
+ tcg_out_insn(s, RIEg, LOCGHI, dest, v3, cc);
} else {
tcg_out_insn(s, RRFc, LOCGR, dest, v3, cc);
}
@@ -1530,6 +1533,7 @@ static void tgen_compare_branch(TCGContext *s, S390Opcode opc, int cc,
TCGReg r1, TCGReg r2, TCGLabel *l)
{
tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2);
+ /* Format RIE-b */
tcg_out16(s, (opc & 0xff00) | (r1 << 4) | r2);
tcg_out16(s, 0);
tcg_out16(s, cc << 12 | (opc & 0xff));
@@ -1539,6 +1543,7 @@ static void tgen_compare_imm_branch(TCGContext *s, S390Opcode opc, int cc,
TCGReg r1, int i2, TCGLabel *l)
{
tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2);
+ /* Format RIE-c */
tcg_out16(s, (opc & 0xff00) | (r1 << 4) | cc);
tcg_out16(s, 0);
tcg_out16(s, (i2 << 8) | (opc & 0xff));
@@ -1558,8 +1563,8 @@ static void tgen_brcond(TCGContext *s, TCGType type, TCGCond c,
if (!c2const) {
opc = (type == TCG_TYPE_I32
- ? (is_unsigned ? RIE_CLRJ : RIE_CRJ)
- : (is_unsigned ? RIE_CLGRJ : RIE_CGRJ));
+ ? (is_unsigned ? RIEb_CLRJ : RIEb_CRJ)
+ : (is_unsigned ? RIEb_CLGRJ : RIEb_CGRJ));
tgen_compare_branch(s, opc, cc, r1, c2, l);
return;
}
@@ -1570,18 +1575,18 @@ static void tgen_brcond(TCGContext *s, TCGType type, TCGCond c,
larger comparison range afforded by COMPARE IMMEDIATE. */
if (type == TCG_TYPE_I32) {
if (is_unsigned) {
- opc = RIE_CLIJ;
+ opc = RIEc_CLIJ;
in_range = (uint32_t)c2 == (uint8_t)c2;
} else {
- opc = RIE_CIJ;
+ opc = RIEc_CIJ;
in_range = (int32_t)c2 == (int8_t)c2;
}
} else {
if (is_unsigned) {
- opc = RIE_CLGIJ;
+ opc = RIEc_CLGIJ;
in_range = (uint64_t)c2 == (uint8_t)c2;
} else {
- opc = RIE_CGIJ;
+ opc = RIEc_CGIJ;
in_range = (int64_t)c2 == (int8_t)c2;
}
}
--
2.34.1
next prev parent reply other threads:[~2022-12-02 6:54 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-02 6:51 [PATCH v3 00/13] tcg/s390x: misc patches Richard Henderson
2022-12-02 6:51 ` [PATCH v3 01/13] tcg/s390x: Use register pair allocation for div and mulu2 Richard Henderson
2022-12-06 15:49 ` Ilya Leoshkevich
2022-12-02 6:51 ` [PATCH v3 02/13] tcg/s390x: Remove TCG_REG_TB Richard Henderson
2022-12-06 19:29 ` Ilya Leoshkevich
2022-12-06 22:22 ` Richard Henderson
2022-12-07 0:42 ` Richard Henderson
2022-12-08 14:04 ` Ilya Leoshkevich
2022-12-07 7:45 ` Thomas Huth
2022-12-07 14:55 ` Richard Henderson
2022-12-07 20:40 ` Ilya Leoshkevich
2022-12-07 21:20 ` Christian Borntraeger
2022-12-07 22:09 ` Ilya Leoshkevich
2022-12-02 6:51 ` [PATCH v3 03/13] tcg/s390x: Use LARL+AGHI for odd addresses Richard Henderson
2022-12-06 19:42 ` Ilya Leoshkevich
2022-12-02 6:51 ` [PATCH v3 04/13] tcg/s390x: Distinguish RRF-a and RRF-c formats Richard Henderson
2022-12-06 19:45 ` Ilya Leoshkevich
2022-12-02 6:51 ` Richard Henderson [this message]
2022-12-06 19:47 ` [PATCH v3 05/13] tcg/s390x: Distinguish RIE formats Ilya Leoshkevich
2022-12-02 6:51 ` [PATCH v3 06/13] tcg/s390x: Support MIE2 multiply single instructions Richard Henderson
2022-12-06 20:02 ` Ilya Leoshkevich
2022-12-06 20:20 ` Richard Henderson
2022-12-02 6:51 ` [PATCH v3 07/13] tcg/s390x: Support MIE2 MGRK instruction Richard Henderson
2022-12-06 20:02 ` Ilya Leoshkevich
2022-12-02 6:51 ` [PATCH v3 08/13] tcg/s390x: Support MIE3 logical operations Richard Henderson
2022-12-06 20:08 ` Ilya Leoshkevich
2022-12-02 6:51 ` [PATCH v3 09/13] tcg/s390x: Create tgen_cmp2 to simplify movcond Richard Henderson
2022-12-06 20:14 ` Ilya Leoshkevich
2022-12-02 6:51 ` [PATCH v3 10/13] tcg/s390x: Generalize movcond implementation Richard Henderson
2022-12-06 20:39 ` Ilya Leoshkevich
2022-12-02 6:51 ` [PATCH v3 11/13] tcg/s390x: Support SELGR instruction in movcond Richard Henderson
2022-12-06 20:41 ` Ilya Leoshkevich
2022-12-02 6:51 ` [PATCH v3 12/13] tcg/s390x: Use tgen_movcond_int in tgen_clz Richard Henderson
2022-12-06 20:49 ` Ilya Leoshkevich
2022-12-02 6:52 ` [PATCH v3 13/13] tcg/s390x: Implement ctpop operation Richard Henderson
2022-12-06 21:10 ` Ilya Leoshkevich
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