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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: r@hev.cc
Subject: [PATCH 05/22] tcg: Replace asserts on tcg_jmp_insn_offset
Date: Mon,  5 Dec 2022 22:16:58 -0600	[thread overview]
Message-ID: <20221206041715.314209-6-richard.henderson@linaro.org> (raw)
In-Reply-To: <20221206041715.314209-1-richard.henderson@linaro.org>

Test TCG_TARGET_HAS_direct_jump instead of testing an
implementation pointer.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/aarch64/tcg-target.c.inc     | 2 +-
 tcg/arm/tcg-target.c.inc         | 2 +-
 tcg/loongarch64/tcg-target.c.inc | 2 +-
 tcg/mips/tcg-target.c.inc        | 2 +-
 tcg/riscv/tcg-target.c.inc       | 2 +-
 tcg/s390x/tcg-target.c.inc       | 2 +-
 tcg/tci/tcg-target.c.inc         | 2 +-
 7 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 16c5e33b69..8e97da3a39 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -1917,7 +1917,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
 
     switch (opc) {
     case INDEX_op_goto_tb:
-        tcg_debug_assert(s->tb_jmp_insn_offset != NULL);
+        qemu_build_assert(TCG_TARGET_HAS_direct_jump);
         /*
          * Ensure that ADRP+ADD are 8-byte aligned so that an atomic
          * write can be used to patch the target address.
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index e5c2eae5a5..31f8c5b7a7 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -1947,7 +1947,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
             intptr_t ptr, dif, dil;
             TCGReg base = TCG_REG_PC;
 
-            tcg_debug_assert(s->tb_jmp_insn_offset == 0);
+            qemu_build_assert(!TCG_TARGET_HAS_direct_jump);
             ptr = (intptr_t)tcg_splitwx_to_rx(s->tb_jmp_target_addr + args[0]);
             dif = tcg_pcrel_diff(s, (void *)ptr) - 8;
             dil = sextract32(dif, 0, 12);
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 41fc5ffa91..78398684cd 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -1089,7 +1089,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
 
     switch (opc) {
     case INDEX_op_goto_tb:
-        tcg_debug_assert(s->tb_jmp_insn_offset != NULL);
+        qemu_build_assert(TCG_TARGET_HAS_direct_jump);
         /*
          * Ensure that patch area is 8-byte aligned so that an
          * atomic write can be used to patch the target address.
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 819648b100..5fc96e4406 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -1986,7 +1986,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
     switch (opc) {
     case INDEX_op_goto_tb:
         /* indirect jump method */
-        tcg_debug_assert(s->tb_jmp_insn_offset == 0);
+        qemu_build_assert(!TCG_TARGET_HAS_direct_jump);
         tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO,
                    (uintptr_t)(s->tb_jmp_target_addr + a0));
         tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 1381c835af..1e8406b8c1 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -1286,7 +1286,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
 
     switch (opc) {
     case INDEX_op_goto_tb:
-        assert(s->tb_jmp_insn_offset == 0);
+        qemu_build_assert(!TCG_TARGET_HAS_direct_jump);
         /* indirect jump method */
         tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_ZERO,
                    (uintptr_t)(s->tb_jmp_target_addr + a0));
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index 9568452773..9498694564 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -2095,7 +2095,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
     switch (opc) {
     case INDEX_op_goto_tb:
         a0 = args[0];
-        if (s->tb_jmp_insn_offset) {
+        if (TCG_TARGET_HAS_direct_jump) {
             /*
              * branch displacement must be aligned for atomic patching;
              * see if we need to add extra nop before branch
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 34583a3499..d1cc41261a 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -606,7 +606,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
 
     switch (opc) {
     case INDEX_op_goto_tb:
-        tcg_debug_assert(s->tb_jmp_insn_offset == 0);
+        qemu_build_assert(!TCG_TARGET_HAS_direct_jump);
         /* indirect jump method. */
         tcg_out_op_p(s, opc, s->tb_jmp_target_addr + args[0]);
         set_jmp_reset_offset(s, args[0]);
-- 
2.34.1



  parent reply	other threads:[~2022-12-06  4:18 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-06  4:16 [PATCH 00/22] tcg: exit_tb tidy, goto_tb reorg Richard Henderson
2022-12-06  4:16 ` [PATCH 01/22] tcg: Split out tcg_out_exit_tb Richard Henderson
2022-12-06  7:24   ` Philippe Mathieu-Daudé
2022-12-06  4:16 ` [PATCH 02/22] tcg/i386: Remove unused goto_tb code for indirect jump Richard Henderson
2022-12-06  4:16 ` [PATCH 03/22] tcg/ppc: " Richard Henderson
2022-12-06  4:16 ` [PATCH 04/22] tcg/sparc64: " Richard Henderson
2022-12-06  4:16 ` Richard Henderson [this message]
2022-12-06  7:27   ` [PATCH 05/22] tcg: Replace asserts on tcg_jmp_insn_offset Philippe Mathieu-Daudé
2022-12-06  4:16 ` [PATCH 06/22] tcg: Introduce set_jmp_insn_offset Richard Henderson
2022-12-06  4:17 ` [PATCH 07/22] tcg: Introduce get_jmp_target_addr Richard Henderson
2022-12-06  7:29   ` Philippe Mathieu-Daudé
2022-12-06  4:17 ` [PATCH 08/22] tcg: Split out tcg_out_goto_tb Richard Henderson
2022-12-06  7:36   ` Philippe Mathieu-Daudé
2022-12-06  4:17 ` [PATCH 09/22] tcg: Rename TB_JMP_RESET_OFFSET_INVALID to TB_JMP_OFFSET_INVALID Richard Henderson
2022-12-06  7:36   ` Philippe Mathieu-Daudé
2022-12-06  4:17 ` [PATCH 10/22] tcg: Add gen_tb to TCGContext Richard Henderson
2022-12-06  4:17 ` [PATCH 11/22] tcg: Add TranslationBlock.jmp_insn_offset Richard Henderson
2022-12-06  4:17 ` [PATCH 12/22] tcg: Change tb_target_set_jmp_target arguments Richard Henderson
2022-12-06  4:17 ` [PATCH 13/22] tcg: Move tb_target_set_jmp_target declaration to tcg.h Richard Henderson
2022-12-06  7:38   ` Philippe Mathieu-Daudé
2022-12-06  4:17 ` [PATCH 14/22] tcg: Always define tb_target_set_jmp_target Richard Henderson
2022-12-06  7:39   ` Philippe Mathieu-Daudé
2022-12-06  4:17 ` [PATCH 15/22] tcg: Remove TCG_TARGET_HAS_direct_jump Richard Henderson
2022-12-06  4:17 ` [PATCH 16/22] tcg/aarch64: Reorg goto_tb implementation Richard Henderson
2022-12-06  4:17 ` [PATCH 17/22] tcg/ppc: " Richard Henderson
2022-12-06  4:17 ` [PATCH 18/22] tcg/sparc64: Remove USE_REG_TB Richard Henderson
2022-12-06  7:44   ` Philippe Mathieu-Daudé
2022-12-06 15:40     ` Richard Henderson
2022-12-06  4:17 ` [PATCH 19/22] tcg/sparc64: Reorg goto_tb implementation Richard Henderson
2022-12-06  4:17 ` [PATCH 20/22] tcg/arm: Implement direct branch for goto_tb Richard Henderson
2022-12-06  4:17 ` [PATCH 21/22] tcg/riscv: Introduce OPC_NOP Richard Henderson
2022-12-06  7:46   ` Philippe Mathieu-Daudé
2022-12-06  4:17 ` [PATCH 22/22] tcg/riscv: Implement direct branch for goto_tb Richard Henderson
2022-12-06  7:48   ` Philippe Mathieu-Daudé
2022-12-06 15:41     ` Richard Henderson

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