From: <tobias.roehmel@rwth-aachen.de>
To: <qemu-devel@nongnu.org>
Cc: peter.maydell@linaro.org,
"Tobias Röhmel" <tobias.roehmel@rwth-aachen.de>
Subject: [PATCH v6 4/7] target/arm: Enable TTBCR_EAE for ARMv8-R AArch32
Date: Tue, 6 Dec 2022 11:25:01 +0100 [thread overview]
Message-ID: <20221206102504.165775-5-tobias.roehmel@rwth-aachen.de> (raw)
In-Reply-To: <20221206102504.165775-1-tobias.roehmel@rwth-aachen.de>
From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
ARMv8-R AArch32 CPUs behave as if TTBCR.EAE is always 1 even
tough they don't have the TTBCR register.
See ARM Architecture Reference Manual Supplement - ARMv8, for the ARMv8-R
AArch32 architecture profile Version:A.c section C1.2.
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/debug_helper.c | 3 +++
target/arm/internals.h | 4 ++++
target/arm/tlb_helper.c | 4 ++++
3 files changed, 11 insertions(+)
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index c21739242c..2f6ddc0da5 100644
--- a/target/arm/debug_helper.c
+++ b/target/arm/debug_helper.c
@@ -437,6 +437,9 @@ static uint32_t arm_debug_exception_fsr(CPUARMState *env)
if (target_el == 2 || arm_el_is_aa64(env, target_el)) {
using_lpae = true;
+ } else if (arm_feature(env, ARM_FEATURE_PMSA) &&
+ arm_feature(env, ARM_FEATURE_V8)) {
+ using_lpae = true;
} else {
if (arm_feature(env, ARM_FEATURE_LPAE) &&
(env->cp15.tcr_el[target_el] & TTBCR_EAE)) {
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 161e42d50f..d9555309df 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -257,6 +257,10 @@ unsigned int arm_pamax(ARMCPU *cpu);
static inline bool extended_addresses_enabled(CPUARMState *env)
{
uint64_t tcr = env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1];
+ if (arm_feature(env, ARM_FEATURE_PMSA) &&
+ arm_feature(env, ARM_FEATURE_V8)) {
+ return true;
+ }
return arm_el_is_aa64(env, 1) ||
(arm_feature(env, ARM_FEATURE_LPAE) && (tcr & TTBCR_EAE));
}
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
index 0f4f4fc809..60abcbebe6 100644
--- a/target/arm/tlb_helper.c
+++ b/target/arm/tlb_helper.c
@@ -19,6 +19,10 @@ bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
if (el == 2 || arm_el_is_aa64(env, el)) {
return true;
}
+ if (arm_feature(env, ARM_FEATURE_PMSA) &&
+ arm_feature(env, ARM_FEATURE_V8)) {
+ return true;
+ }
if (arm_feature(env, ARM_FEATURE_LPAE)
&& (regime_tcr(env, mmu_idx) & TTBCR_EAE)) {
return true;
--
2.34.1
next prev parent reply other threads:[~2022-12-06 10:26 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-06 10:24 [PATCH v6 0/7] Add ARM Cortex-R52 CPU tobias.roehmel
2022-12-06 10:24 ` [PATCH v6 1/7] target/arm: Don't add all MIDR aliases for cores that implement PMSA tobias.roehmel
2022-12-06 10:24 ` [PATCH v6 2/7] target/arm: Make RVBAR available for all ARMv8 CPUs tobias.roehmel
2022-12-06 10:25 ` [PATCH v6 3/7] target/arm: Make stage_2_format for cache attributes optional tobias.roehmel
2022-12-06 10:25 ` tobias.roehmel [this message]
2022-12-06 10:25 ` [PATCH v6 5/7] target/arm: Add PMSAv8r registers tobias.roehmel
2022-12-06 10:25 ` [PATCH v6 6/7] target/arm: Add PMSAv8r functionality tobias.roehmel
2022-12-06 10:25 ` [PATCH v6 7/7] target/arm: Add ARM Cortex-R52 CPU tobias.roehmel
2022-12-06 10:39 ` [PATCH v6 0/7] " Philippe Mathieu-Daudé
2022-12-06 11:43 ` Tobias Roehmel
2022-12-06 12:00 ` Philippe Mathieu-Daudé
2022-12-19 17:05 ` Peter Maydell
2022-12-27 7:34 ` Tobias Röhmel
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