From: Bin Meng <bmeng@tinylab.org>
To: qemu-devel@nongnu.org
Cc: Alistair Francis <alistair.francis@wdc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
qemu-riscv@nongnu.org
Subject: [PATCH v2 09/16] hw/intc: sifive_plic: Update "num-sources" property default value
Date: Wed, 7 Dec 2022 18:03:28 +0800 [thread overview]
Message-ID: <20221207100335.290481-9-bmeng@tinylab.org> (raw)
In-Reply-To: <20221207100335.290481-1-bmeng@tinylab.org>
At present the default value of "num-sources" property is zero,
which does not make a lot of sense, as in sifive_plic_realize()
we see s->bitfield_words is calculated by:
s->bitfield_words = (s->num_sources + 31) >> 5;
if the we don't configure "num-sources" property its default value
zero makes s->bitfield_words zero too, which isn't true because
interrupt source 0 still occupies one word.
Let's change the default value to 1 meaning that only interrupt
source 0 is supported by default and a sanity check in realize().
While we are here, add a comment to describe the exact meaning of
this property that the number should include interrupt source 0.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
Changes in v2:
- use error_setg() to propagate the error up via errp instead
hw/intc/sifive_plic.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 9cb4c6d6d4..1edeb1e1ed 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -363,6 +363,11 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
parse_hart_config(s);
+ if (!s->num_sources) {
+ error_setg(errp, "plic: invalid number of interrupt sources");
+ return;
+ }
+
s->bitfield_words = (s->num_sources + 31) >> 5;
s->num_enables = s->bitfield_words * s->num_addrs;
s->source_priority = g_new0(uint32_t, s->num_sources);
@@ -420,7 +425,8 @@ static const VMStateDescription vmstate_sifive_plic = {
static Property sifive_plic_properties[] = {
DEFINE_PROP_STRING("hart-config", SiFivePLICState, hart_config),
DEFINE_PROP_UINT32("hartid-base", SiFivePLICState, hartid_base, 0),
- DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 0),
+ /* number of interrupt sources including interrupt source 0 */
+ DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 1),
DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0),
DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0),
DEFINE_PROP_UINT32("pending-base", SiFivePLICState, pending_base, 0),
--
2.34.1
next prev parent reply other threads:[~2022-12-07 10:06 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-07 10:03 [PATCH v2 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Bin Meng
2022-12-07 10:03 ` [PATCH v2 02/16] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers Bin Meng
2022-12-08 10:38 ` Philippe Mathieu-Daudé
2022-12-07 10:03 ` [PATCH v2 03/16] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC Bin Meng
2022-12-07 10:03 ` [PATCH v2 04/16] hw/riscv: Sort machines Kconfig options in alphabetical order Bin Meng
2022-12-08 10:40 ` Philippe Mathieu-Daudé
2022-12-08 22:45 ` Wilfred Mallawa
2022-12-07 10:03 ` [PATCH v2 05/16] hw/riscv: spike: Remove misleading comments Bin Meng
2022-12-07 10:03 ` [PATCH v2 06/16] hw/intc: sifive_plic: Drop PLICMode_H Bin Meng
2022-12-07 10:03 ` [PATCH v2 07/16] hw/intc: sifive_plic: Improve robustness of the PLIC config parser Bin Meng
2022-12-07 10:03 ` [PATCH v2 08/16] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize() Bin Meng
2022-12-08 4:18 ` Alistair Francis
2022-12-08 10:40 ` Philippe Mathieu-Daudé
2022-12-07 10:03 ` Bin Meng [this message]
2022-12-07 10:03 ` [PATCH v2 10/16] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC Bin Meng
2022-12-07 10:03 ` [PATCH v2 11/16] hw/riscv: sifive_e: " Bin Meng
2022-12-07 10:03 ` [PATCH v2 12/16] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev" Bin Meng
2022-12-07 10:03 ` [PATCH v2 13/16] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb Bin Meng
2022-12-07 10:03 ` [PATCH v2 14/16] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0 Bin Meng
2022-12-08 22:49 ` Wilfred Mallawa
2022-12-07 10:03 ` [PATCH v2 15/16] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization Bin Meng
2022-12-07 10:03 ` [PATCH v2 16/16] hw/intc: sifive_plic: Fix the pending register range check Bin Meng
2022-12-08 10:38 ` [PATCH v2 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Philippe Mathieu-Daudé
2022-12-08 22:46 ` Wilfred Mallawa
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