From: Xiaoyao Li <xiaoyao.li@intel.com>
To: Paolo Bonzini <pbonzini@redhat.com>,
Marcelo Tosatti <mtosatti@redhat.com>
Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, xiaoyao.li@intel.com
Subject: [PATCH v3 2/8] target/i386/intel-pt: Fix INTEL_PT_ADDR_RANGES_NUM_MASK
Date: Thu, 8 Dec 2022 14:25:07 +0800 [thread overview]
Message-ID: <20221208062513.2589476-3-xiaoyao.li@intel.com> (raw)
In-Reply-To: <20221208062513.2589476-1-xiaoyao.li@intel.com>
Per Intel SDM, bits 2:0 of CPUID(0x14,0x1).EAX indicate the number of
address ranges for INTEL-PT.
Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
---
target/i386/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 8d95202f6a42..9ae36639d380 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -570,7 +570,7 @@ static CPUCacheInfo legacy_l3_cache = {
/* generated packets which contain IP payloads have LIP values */
#define INTEL_PT_IP_LIP (1 << 31)
#define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
-#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
+#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x7
#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
--
2.27.0
next prev parent reply other threads:[~2022-12-08 6:27 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-08 6:25 [PATCH v3 0/8] Make Intel PT configurable Xiaoyao Li
2022-12-08 6:25 ` [PATCH v3 1/8] target/i386: Print CPUID subleaf info for unsupported feature Xiaoyao Li
2022-12-08 6:25 ` Xiaoyao Li [this message]
2022-12-08 6:25 ` [PATCH v3 3/8] target/i386/intel-pt: Introduce FeatureWordInfo for Intel PT CPUID leaf 0x14 Xiaoyao Li
2022-12-08 6:25 ` [PATCH v3 4/8] target/i386/intel-pt: print special message for INTEL_PT_ADDR_RANGES_NUM Xiaoyao Li
2022-12-09 6:43 ` Chenyi Qiang
2022-12-13 12:09 ` Xiaoyao Li
2022-12-14 1:48 ` Chenyi Qiang
2022-12-08 6:25 ` [PATCH v3 5/8] target/i386/intel-pt: Rework/rename the default INTEL-PT feature set Xiaoyao Li
2022-12-08 6:25 ` [PATCH v3 6/8] target/i386/intel-pt: Enable host pass through of Intel PT Xiaoyao Li
2022-12-09 6:55 ` Chenyi Qiang
2022-12-13 12:15 ` Xiaoyao Li
2023-02-21 5:14 ` Wang, Lei
2023-02-21 9:37 ` Xiaoyao Li
2022-12-08 6:25 ` [PATCH v3 7/8] target/i386/intel-pt: Define specific PT feature set for IceLake-server and Snowridge Xiaoyao Li
2022-12-09 7:11 ` Chenyi Qiang
2022-12-08 6:25 ` [PATCH v3 8/8] target/i386/intel-pt: Access MSR_IA32_RTIT_ADDRn based on guest CPUID configuration Xiaoyao Li
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20221208062513.2589476-3-xiaoyao.li@intel.com \
--to=xiaoyao.li@intel.com \
--cc=kvm@vger.kernel.org \
--cc=mtosatti@redhat.com \
--cc=pbonzini@redhat.com \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).