From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Paolo Bonzini" <pbonzini@redhat.com>,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"Bernhard Beschow" <shentey@gmail.com>,
"Daniel P. Berrangé" <berrange@redhat.com>,
"Thomas Huth" <thuth@redhat.com>,
"Marc-André Lureau" <marcandre.lureau@redhat.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Aurelien Jarno" <aurelien@aurel32.net>
Subject: [PATCH-for-8.0 3/7] hw/mips/gt64xxx_pci: Manage endian bits with the RegisterField API
Date: Fri, 9 Dec 2022 16:15:29 +0100 [thread overview]
Message-ID: <20221209151533.69516-4-philmd@linaro.org> (raw)
In-Reply-To: <20221209151533.69516-1-philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/mips/gt64xxx_pci.c | 37 +++++++++++++++++++++++++------------
1 file changed, 25 insertions(+), 12 deletions(-)
diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
index 1b9ac7f792..8c9ec80f7c 100644
--- a/hw/mips/gt64xxx_pci.c
+++ b/hw/mips/gt64xxx_pci.c
@@ -26,6 +26,7 @@
#include "qapi/error.h"
#include "qemu/units.h"
#include "qemu/log.h"
+#include "hw/registerfields.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
#include "hw/misc/empty_slot.h"
@@ -41,6 +42,9 @@
#define GT_CPU (0x000 >> 2)
#define GT_MULTI (0x120 >> 2)
+REG32(GT_CPU, 0x000)
+FIELD(GT_CPU, Endianess, 12, 1)
+
/* CPU Address Decode */
#define GT_SCS10LD (0x008 >> 2)
#define GT_SCS10HD (0x010 >> 2)
@@ -210,6 +214,13 @@
#define GT_PCI0_CFGADDR (0xcf8 >> 2)
#define GT_PCI0_CFGDATA (0xcfc >> 2)
+REG32(GT_PCI0_CMD, 0xc00)
+FIELD(GT_PCI0_CMD, MByteSwap, 0, 1)
+FIELD(GT_PCI0_CMD, SByteSwap, 16, 1)
+REG32(GT_PCI1_CMD, 0xc80)
+FIELD(GT_PCI1_CMD, MByteSwap, 0, 1)
+FIELD(GT_PCI1_CMD, SByteSwap, 16, 1)
+
/* Interrupts */
#define GT_INTRCAUSE (0xc18 >> 2)
#define GT_INTRMASK (0xc1c >> 2)
@@ -983,15 +994,17 @@ static const MemoryRegionOps isd_mem_ops = {
static void gt64120_reset(DeviceState *dev)
{
GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev);
+#if TARGET_BIG_ENDIAN
+ unsigned cpu_le = 0;
+#else
+ unsigned cpu_le = 1;
+#endif
/* FIXME: Malta specific hw assumptions ahead */
/* CPU Configuration */
-#if TARGET_BIG_ENDIAN
s->regs[GT_CPU] = 0x00000000;
-#else
- s->regs[GT_CPU] = 0x00001000;
-#endif
+ s->regs[GT_CPU] = FIELD_DP32(s->regs[GT_CPU], GT_CPU, Endianess, cpu_le);
s->regs[GT_MULTI] = 0x00000003;
/* CPU Address decode */
@@ -1098,11 +1111,11 @@ static void gt64120_reset(DeviceState *dev)
s->regs[GT_TC_CONTROL] = 0x00000000;
/* PCI Internal */
-#if TARGET_BIG_ENDIAN
s->regs[GT_PCI0_CMD] = 0x00000000;
-#else
- s->regs[GT_PCI0_CMD] = 0x00010001;
-#endif
+ s->regs[GT_PCI0_CMD] = FIELD_DP32(s->regs[GT_PCI0_CMD],
+ GT_PCI0_CMD, MByteSwap, cpu_le);
+ s->regs[GT_PCI0_CMD] = FIELD_DP32(s->regs[GT_PCI0_CMD],
+ GT_PCI0_CMD, SByteSwap, cpu_le);
s->regs[GT_PCI0_TOR] = 0x0000070f;
s->regs[GT_PCI0_BS_SCS10] = 0x00fff000;
s->regs[GT_PCI0_BS_SCS32] = 0x00fff000;
@@ -1119,11 +1132,11 @@ static void gt64120_reset(DeviceState *dev)
s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000;
s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000;
s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000;
-#if TARGET_BIG_ENDIAN
s->regs[GT_PCI1_CMD] = 0x00000000;
-#else
- s->regs[GT_PCI1_CMD] = 0x00010001;
-#endif
+ s->regs[GT_PCI1_CMD] = FIELD_DP32(s->regs[GT_PCI1_CMD],
+ GT_PCI1_CMD, MByteSwap, cpu_le);
+ s->regs[GT_PCI1_CMD] = FIELD_DP32(s->regs[GT_PCI1_CMD],
+ GT_PCI1_CMD, SByteSwap, cpu_le);
s->regs[GT_PCI1_TOR] = 0x0000070f;
s->regs[GT_PCI1_BS_SCS10] = 0x00fff000;
s->regs[GT_PCI1_BS_SCS32] = 0x00fff000;
--
2.38.1
next prev parent reply other threads:[~2022-12-09 15:18 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-09 15:15 [PATCH-for-8.0 0/7] hw/mips: Make gt64xxx_pci.c endian-agnostic Philippe Mathieu-Daudé
2022-12-09 15:15 ` [PATCH-for-8.0 1/7] hw/mips/Kconfig: Introduce CONFIG_GT64120 to select gt64xxx_pci.c Philippe Mathieu-Daudé
2022-12-12 0:13 ` Bernhard Beschow
2022-12-12 8:02 ` Philippe Mathieu-Daudé
2022-12-12 20:11 ` Bernhard Beschow
2022-12-20 0:48 ` Richard Henderson
2022-12-09 15:15 ` [PATCH-for-8.0 2/7] hw/mips/gt64xxx_pci: Let the GT64120 manage the lower 512MiB hole Philippe Mathieu-Daudé
2022-12-20 0:48 ` Richard Henderson
2022-12-09 15:15 ` Philippe Mathieu-Daudé [this message]
2022-12-20 0:51 ` [PATCH-for-8.0 3/7] hw/mips/gt64xxx_pci: Manage endian bits with the RegisterField API Richard Henderson
2022-12-09 15:15 ` [PATCH-for-8.0 4/7] hw/mips/gt64xxx_pci: Add a 'cpu-little-endian' qdev property Philippe Mathieu-Daudé
2022-12-20 0:52 ` Richard Henderson
2022-12-20 8:06 ` Philippe Mathieu-Daudé
2022-12-09 15:15 ` [PATCH-for-8.0 5/7] hw/mips/malta: Explicit GT64120 endianness upon device creation Philippe Mathieu-Daudé
2022-12-20 0:52 ` Richard Henderson
2022-12-20 8:30 ` Philippe Mathieu-Daudé
2022-12-20 11:32 ` Philippe Mathieu-Daudé
2022-12-09 15:15 ` [PATCH-for-8.0 6/7] hw/mips/meson: Make gt64xxx_pci.c endian-agnostic Philippe Mathieu-Daudé
2022-12-20 0:53 ` Richard Henderson
2022-12-09 15:15 ` [PATCH-for-8.0 7/7] hw/mips/gt64xxx_pci: Move it to hw/pci-host/ Philippe Mathieu-Daudé
2022-12-12 0:02 ` Bernhard Beschow
2022-12-20 0:55 ` Richard Henderson
2022-12-12 0:55 ` [PATCH-for-8.0 0/7] hw/mips: Make gt64xxx_pci.c endian-agnostic Bernhard Beschow
2022-12-12 7:30 ` Philippe Mathieu-Daudé
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