From: Bin Meng <bmeng@tinylab.org>
To: qemu-devel@nongnu.org
Cc: Wilfred Mallawa <wilfred.mallawa@wdc.com>,
Alistair Francis <alistair.francis@wdc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
qemu-riscv@nongnu.org
Subject: [PATCH v3 11/16] hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC
Date: Sun, 11 Dec 2022 11:08:24 +0800 [thread overview]
Message-ID: <20221211030829.802437-11-bmeng@tinylab.org> (raw)
In-Reply-To: <20221211030829.802437-1-bmeng@tinylab.org>
Per chapter 10 in Freedom E310 manuals [1][2][3], E310 G002 and G003
supports 52 interrupt sources while G000 supports 51 interrupt sources.
We use the value of G002 and G003, so it is 53 (including source 0).
[1] G000 manual:
https://sifive.cdn.prismic.io/sifive/4faf3e34-4a42-4c2f-be9e-c77baa4928c7_fe310-g000-manual-v3p2.pdf
[2] G002 manual:
https://sifive.cdn.prismic.io/sifive/034760b5-ac6a-4b1c-911c-f4148bb2c4a5_fe310-g002-v1p5.pdf
[3] G003 manual:
https://sifive.cdn.prismic.io/sifive/3af39c59-6498-471e-9dab-5355a0d539eb_fe310-g003-manual.pdf
Fixes: eb637edb1241 ("SiFive Freedom E Series RISC-V Machine")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v1)
include/hw/riscv/sifive_e.h | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
index d738745925..9e58247fd8 100644
--- a/include/hw/riscv/sifive_e.h
+++ b/include/hw/riscv/sifive_e.h
@@ -82,7 +82,12 @@ enum {
};
#define SIFIVE_E_PLIC_HART_CONFIG "M"
-#define SIFIVE_E_PLIC_NUM_SOURCES 127
+/*
+ * Freedom E310 G002 and G003 supports 52 interrupt sources while
+ * Freedom E310 G000 supports 51 interrupt sources. We use the value
+ * of G002 and G003, so it is 53 (including interrupt source 0).
+ */
+#define SIFIVE_E_PLIC_NUM_SOURCES 53
#define SIFIVE_E_PLIC_NUM_PRIORITIES 7
#define SIFIVE_E_PLIC_PRIORITY_BASE 0x04
#define SIFIVE_E_PLIC_PENDING_BASE 0x1000
--
2.34.1
next prev parent reply other threads:[~2022-12-11 3:20 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-11 3:08 [PATCH v3 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Bin Meng
2022-12-11 3:08 ` [PATCH v3 02/16] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers Bin Meng
2022-12-11 3:08 ` [PATCH v3 03/16] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC Bin Meng
2022-12-11 3:08 ` [PATCH v3 04/16] hw/riscv: Sort machines Kconfig options in alphabetical order Bin Meng
2022-12-11 3:08 ` [PATCH v3 05/16] hw/riscv: spike: Remove misleading comments Bin Meng
2022-12-11 3:08 ` [PATCH v3 06/16] hw/intc: sifive_plic: Drop PLICMode_H Bin Meng
2022-12-11 3:08 ` [PATCH v3 07/16] hw/intc: sifive_plic: Improve robustness of the PLIC config parser Bin Meng
2022-12-11 3:08 ` [PATCH v3 08/16] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize() Bin Meng
2022-12-11 3:08 ` [PATCH v3 09/16] hw/intc: sifive_plic: Update "num-sources" property default value Bin Meng
2022-12-11 3:08 ` [PATCH v3 10/16] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC Bin Meng
2022-12-11 3:08 ` Bin Meng [this message]
2022-12-11 3:08 ` [PATCH v3 12/16] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev" Bin Meng
2022-12-11 3:08 ` [PATCH v3 13/16] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb Bin Meng
2022-12-11 3:08 ` [PATCH v3 14/16] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0 Bin Meng
2022-12-11 3:08 ` [PATCH v3 15/16] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization Bin Meng
2022-12-12 5:45 ` Alistair Francis
2022-12-11 3:08 ` [PATCH v3 16/16] hw/intc: sifive_plic: Fix the pending register range check Bin Meng
2022-12-12 6:11 ` Alistair Francis
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