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From: Bin Meng <bmeng@tinylab.org>
To: qemu-devel@nongnu.org
Cc: Wilfred Mallawa <wilfred.mallawa@wdc.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Bin Meng <bin.meng@windriver.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	qemu-riscv@nongnu.org
Subject: [PATCH v3 12/16] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev"
Date: Sun, 11 Dec 2022 11:08:25 +0800	[thread overview]
Message-ID: <20221211030829.802437-12-bmeng@tinylab.org> (raw)
In-Reply-To: <20221211030829.802437-1-bmeng@tinylab.org>

At present magic number is used to create "riscv,ndev" property
in the dtb. Let's use the macro SIFIVE_U_PLIC_NUM_SOURCES that
is used to instantiate the PLIC model instead.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---

(no changes since v1)

 hw/riscv/sifive_u.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index b139824aab..b40a4767e2 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -287,7 +287,8 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
     qemu_fdt_setprop_cells(fdt, nodename, "reg",
         0x0, memmap[SIFIVE_U_DEV_PLIC].base,
         0x0, memmap[SIFIVE_U_DEV_PLIC].size);
-    qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
+    qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev",
+                          SIFIVE_U_PLIC_NUM_SOURCES - 1);
     qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
     plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
     g_free(cells);
-- 
2.34.1



  parent reply	other threads:[~2022-12-11  3:24 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-11  3:08 [PATCH v3 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Bin Meng
2022-12-11  3:08 ` [PATCH v3 02/16] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers Bin Meng
2022-12-11  3:08 ` [PATCH v3 03/16] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC Bin Meng
2022-12-11  3:08 ` [PATCH v3 04/16] hw/riscv: Sort machines Kconfig options in alphabetical order Bin Meng
2022-12-11  3:08 ` [PATCH v3 05/16] hw/riscv: spike: Remove misleading comments Bin Meng
2022-12-11  3:08 ` [PATCH v3 06/16] hw/intc: sifive_plic: Drop PLICMode_H Bin Meng
2022-12-11  3:08 ` [PATCH v3 07/16] hw/intc: sifive_plic: Improve robustness of the PLIC config parser Bin Meng
2022-12-11  3:08 ` [PATCH v3 08/16] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize() Bin Meng
2022-12-11  3:08 ` [PATCH v3 09/16] hw/intc: sifive_plic: Update "num-sources" property default value Bin Meng
2022-12-11  3:08 ` [PATCH v3 10/16] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC Bin Meng
2022-12-11  3:08 ` [PATCH v3 11/16] hw/riscv: sifive_e: " Bin Meng
2022-12-11  3:08 ` Bin Meng [this message]
2022-12-11  3:08 ` [PATCH v3 13/16] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb Bin Meng
2022-12-11  3:08 ` [PATCH v3 14/16] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0 Bin Meng
2022-12-11  3:08 ` [PATCH v3 15/16] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization Bin Meng
2022-12-12  5:45   ` Alistair Francis
2022-12-11  3:08 ` [PATCH v3 16/16] hw/intc: sifive_plic: Fix the pending register range check Bin Meng
2022-12-12  6:11   ` Alistair Francis

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