From: Bin Meng <bmeng@tinylab.org>
To: qemu-devel@nongnu.org
Cc: "Alistair Francis" <alistair.francis@wdc.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Wilfred Mallawa" <wilfred.mallawa@wdc.com>,
"Bin Meng" <bin.meng@windriver.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
qemu-riscv@nongnu.org
Subject: [PATCH v3 04/16] hw/riscv: Sort machines Kconfig options in alphabetical order
Date: Sun, 11 Dec 2022 11:08:17 +0800 [thread overview]
Message-ID: <20221211030829.802437-4-bmeng@tinylab.org> (raw)
In-Reply-To: <20221211030829.802437-1-bmeng@tinylab.org>
SHAKTI_C machine Kconfig option was inserted in disorder. Fix it.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
---
(no changes since v1)
hw/riscv/Kconfig | 16 +++++++++-------
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 1e4b58024f..4550b3b938 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -4,6 +4,8 @@ config RISCV_NUMA
config IBEX
bool
+# RISC-V machines in alphabetical order
+
config MICROCHIP_PFSOC
bool
select CADENCE_SDHCI
@@ -22,13 +24,6 @@ config OPENTITAN
select SIFIVE_PLIC
select UNIMP
-config SHAKTI_C
- bool
- select UNIMP
- select SHAKTI_UART
- select RISCV_ACLINT
- select SIFIVE_PLIC
-
config RISCV_VIRT
bool
imply PCI_DEVICES
@@ -50,6 +45,13 @@ config RISCV_VIRT
select FW_CFG_DMA
select PLATFORM_BUS
+config SHAKTI_C
+ bool
+ select RISCV_ACLINT
+ select SHAKTI_UART
+ select SIFIVE_PLIC
+ select UNIMP
+
config SIFIVE_E
bool
select RISCV_ACLINT
--
2.34.1
next prev parent reply other threads:[~2022-12-11 3:17 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-11 3:08 [PATCH v3 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Bin Meng
2022-12-11 3:08 ` [PATCH v3 02/16] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers Bin Meng
2022-12-11 3:08 ` [PATCH v3 03/16] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC Bin Meng
2022-12-11 3:08 ` Bin Meng [this message]
2022-12-11 3:08 ` [PATCH v3 05/16] hw/riscv: spike: Remove misleading comments Bin Meng
2022-12-11 3:08 ` [PATCH v3 06/16] hw/intc: sifive_plic: Drop PLICMode_H Bin Meng
2022-12-11 3:08 ` [PATCH v3 07/16] hw/intc: sifive_plic: Improve robustness of the PLIC config parser Bin Meng
2022-12-11 3:08 ` [PATCH v3 08/16] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize() Bin Meng
2022-12-11 3:08 ` [PATCH v3 09/16] hw/intc: sifive_plic: Update "num-sources" property default value Bin Meng
2022-12-11 3:08 ` [PATCH v3 10/16] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC Bin Meng
2022-12-11 3:08 ` [PATCH v3 11/16] hw/riscv: sifive_e: " Bin Meng
2022-12-11 3:08 ` [PATCH v3 12/16] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev" Bin Meng
2022-12-11 3:08 ` [PATCH v3 13/16] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb Bin Meng
2022-12-11 3:08 ` [PATCH v3 14/16] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0 Bin Meng
2022-12-11 3:08 ` [PATCH v3 15/16] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization Bin Meng
2022-12-12 5:45 ` Alistair Francis
2022-12-11 3:08 ` [PATCH v3 16/16] hw/intc: sifive_plic: Fix the pending register range check Bin Meng
2022-12-12 6:11 ` Alistair Francis
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