From: Bin Meng <bmeng@tinylab.org>
To: qemu-devel@nongnu.org
Cc: Wilfred Mallawa <wilfred.mallawa@wdc.com>,
Alistair Francis <alistair.francis@wdc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
qemu-riscv@nongnu.org
Subject: [PATCH v3 06/16] hw/intc: sifive_plic: Drop PLICMode_H
Date: Sun, 11 Dec 2022 11:08:19 +0800 [thread overview]
Message-ID: <20221211030829.802437-6-bmeng@tinylab.org> (raw)
In-Reply-To: <20221211030829.802437-1-bmeng@tinylab.org>
H-mode has been removed since priv spec 1.10. Drop it.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v1)
include/hw/intc/sifive_plic.h | 1 -
hw/intc/sifive_plic.c | 1 -
2 files changed, 2 deletions(-)
diff --git a/include/hw/intc/sifive_plic.h b/include/hw/intc/sifive_plic.h
index 134cf39a96..d3f45ec248 100644
--- a/include/hw/intc/sifive_plic.h
+++ b/include/hw/intc/sifive_plic.h
@@ -33,7 +33,6 @@ DECLARE_INSTANCE_CHECKER(SiFivePLICState, SIFIVE_PLIC,
typedef enum PLICMode {
PLICMode_U,
PLICMode_S,
- PLICMode_H,
PLICMode_M
} PLICMode;
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 0c7696520d..936dcf74bc 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -42,7 +42,6 @@ static PLICMode char_to_mode(char c)
switch (c) {
case 'U': return PLICMode_U;
case 'S': return PLICMode_S;
- case 'H': return PLICMode_H;
case 'M': return PLICMode_M;
default:
error_report("plic: invalid mode '%c'", c);
--
2.34.1
next prev parent reply other threads:[~2022-12-11 3:17 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-11 3:08 [PATCH v3 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Bin Meng
2022-12-11 3:08 ` [PATCH v3 02/16] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers Bin Meng
2022-12-11 3:08 ` [PATCH v3 03/16] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC Bin Meng
2022-12-11 3:08 ` [PATCH v3 04/16] hw/riscv: Sort machines Kconfig options in alphabetical order Bin Meng
2022-12-11 3:08 ` [PATCH v3 05/16] hw/riscv: spike: Remove misleading comments Bin Meng
2022-12-11 3:08 ` Bin Meng [this message]
2022-12-11 3:08 ` [PATCH v3 07/16] hw/intc: sifive_plic: Improve robustness of the PLIC config parser Bin Meng
2022-12-11 3:08 ` [PATCH v3 08/16] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize() Bin Meng
2022-12-11 3:08 ` [PATCH v3 09/16] hw/intc: sifive_plic: Update "num-sources" property default value Bin Meng
2022-12-11 3:08 ` [PATCH v3 10/16] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC Bin Meng
2022-12-11 3:08 ` [PATCH v3 11/16] hw/riscv: sifive_e: " Bin Meng
2022-12-11 3:08 ` [PATCH v3 12/16] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev" Bin Meng
2022-12-11 3:08 ` [PATCH v3 13/16] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb Bin Meng
2022-12-11 3:08 ` [PATCH v3 14/16] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0 Bin Meng
2022-12-11 3:08 ` [PATCH v3 15/16] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization Bin Meng
2022-12-12 5:45 ` Alistair Francis
2022-12-11 3:08 ` [PATCH v3 16/16] hw/intc: sifive_plic: Fix the pending register range check Bin Meng
2022-12-12 6:11 ` Alistair Francis
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