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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-s390x@nongnu.org, Ilya Leoshkevich <iii@linux.ibm.com>
Subject: [PATCH v2 02/27] target/s390x: Use tcg_constant_* for DisasCompare
Date: Sun, 11 Dec 2022 09:27:37 -0600	[thread overview]
Message-ID: <20221211152802.923900-3-richard.henderson@linaro.org> (raw)
In-Reply-To: <20221211152802.923900-1-richard.henderson@linaro.org>

The a and b fields are not modified by the consumer,
and while we need not free a constant, tcg will quietly
ignore such frees, so free_compare need not be changed.

Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/s390x/tcg/translate.c | 44 ++++++++++++++++++------------------
 1 file changed, 22 insertions(+), 22 deletions(-)

diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 4fb396b557..77919295d3 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -830,7 +830,7 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
         c->is_64 = false;
         c->u.s32.a = tcg_temp_new_i32();
         tcg_gen_extrl_i64_i32(c->u.s32.a, cc_dst);
-        c->u.s32.b = tcg_const_i32(0);
+        c->u.s32.b = tcg_constant_i32(0);
         break;
     case CC_OP_LTGT_32:
     case CC_OP_LTUGTU_32:
@@ -845,7 +845,7 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
     case CC_OP_NZ:
     case CC_OP_FLOGR:
         c->u.s64.a = cc_dst;
-        c->u.s64.b = tcg_const_i64(0);
+        c->u.s64.b = tcg_constant_i64(0);
         c->g1 = true;
         break;
     case CC_OP_LTGT_64:
@@ -859,14 +859,14 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
     case CC_OP_TM_64:
     case CC_OP_ICM:
         c->u.s64.a = tcg_temp_new_i64();
-        c->u.s64.b = tcg_const_i64(0);
+        c->u.s64.b = tcg_constant_i64(0);
         tcg_gen_and_i64(c->u.s64.a, cc_src, cc_dst);
         break;
 
     case CC_OP_ADDU:
     case CC_OP_SUBU:
         c->is_64 = true;
-        c->u.s64.b = tcg_const_i64(0);
+        c->u.s64.b = tcg_constant_i64(0);
         c->g1 = true;
         switch (mask) {
         case 8 | 2:
@@ -889,65 +889,65 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
         switch (mask) {
         case 0x8 | 0x4 | 0x2: /* cc != 3 */
             cond = TCG_COND_NE;
-            c->u.s32.b = tcg_const_i32(3);
+            c->u.s32.b = tcg_constant_i32(3);
             break;
         case 0x8 | 0x4 | 0x1: /* cc != 2 */
             cond = TCG_COND_NE;
-            c->u.s32.b = tcg_const_i32(2);
+            c->u.s32.b = tcg_constant_i32(2);
             break;
         case 0x8 | 0x2 | 0x1: /* cc != 1 */
             cond = TCG_COND_NE;
-            c->u.s32.b = tcg_const_i32(1);
+            c->u.s32.b = tcg_constant_i32(1);
             break;
         case 0x8 | 0x2: /* cc == 0 || cc == 2 => (cc & 1) == 0 */
             cond = TCG_COND_EQ;
             c->g1 = false;
             c->u.s32.a = tcg_temp_new_i32();
-            c->u.s32.b = tcg_const_i32(0);
+            c->u.s32.b = tcg_constant_i32(0);
             tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
             break;
         case 0x8 | 0x4: /* cc < 2 */
             cond = TCG_COND_LTU;
-            c->u.s32.b = tcg_const_i32(2);
+            c->u.s32.b = tcg_constant_i32(2);
             break;
         case 0x8: /* cc == 0 */
             cond = TCG_COND_EQ;
-            c->u.s32.b = tcg_const_i32(0);
+            c->u.s32.b = tcg_constant_i32(0);
             break;
         case 0x4 | 0x2 | 0x1: /* cc != 0 */
             cond = TCG_COND_NE;
-            c->u.s32.b = tcg_const_i32(0);
+            c->u.s32.b = tcg_constant_i32(0);
             break;
         case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */
             cond = TCG_COND_NE;
             c->g1 = false;
             c->u.s32.a = tcg_temp_new_i32();
-            c->u.s32.b = tcg_const_i32(0);
+            c->u.s32.b = tcg_constant_i32(0);
             tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
             break;
         case 0x4: /* cc == 1 */
             cond = TCG_COND_EQ;
-            c->u.s32.b = tcg_const_i32(1);
+            c->u.s32.b = tcg_constant_i32(1);
             break;
         case 0x2 | 0x1: /* cc > 1 */
             cond = TCG_COND_GTU;
-            c->u.s32.b = tcg_const_i32(1);
+            c->u.s32.b = tcg_constant_i32(1);
             break;
         case 0x2: /* cc == 2 */
             cond = TCG_COND_EQ;
-            c->u.s32.b = tcg_const_i32(2);
+            c->u.s32.b = tcg_constant_i32(2);
             break;
         case 0x1: /* cc == 3 */
             cond = TCG_COND_EQ;
-            c->u.s32.b = tcg_const_i32(3);
+            c->u.s32.b = tcg_constant_i32(3);
             break;
         default:
             /* CC is masked by something else: (8 >> cc) & mask.  */
             cond = TCG_COND_NE;
             c->g1 = false;
-            c->u.s32.a = tcg_const_i32(8);
-            c->u.s32.b = tcg_const_i32(0);
-            tcg_gen_shr_i32(c->u.s32.a, c->u.s32.a, cc_op);
+            c->u.s32.a = tcg_temp_new_i32();
+            c->u.s32.b = tcg_constant_i32(0);
+            tcg_gen_shr_i32(c->u.s32.a, tcg_constant_i32(8), cc_op);
             tcg_gen_andi_i32(c->u.s32.a, c->u.s32.a, mask);
             break;
         }
@@ -1604,7 +1604,7 @@ static DisasJumpType op_bct32(DisasContext *s, DisasOps *o)
     tcg_gen_subi_i64(t, regs[r1], 1);
     store_reg32_i64(r1, t);
     c.u.s32.a = tcg_temp_new_i32();
-    c.u.s32.b = tcg_const_i32(0);
+    c.u.s32.b = tcg_constant_i32(0);
     tcg_gen_extrl_i64_i32(c.u.s32.a, t);
     tcg_temp_free_i64(t);
 
@@ -1628,7 +1628,7 @@ static DisasJumpType op_bcth(DisasContext *s, DisasOps *o)
     tcg_gen_subi_i64(t, t, 1);
     store_reg32h_i64(r1, t);
     c.u.s32.a = tcg_temp_new_i32();
-    c.u.s32.b = tcg_const_i32(0);
+    c.u.s32.b = tcg_constant_i32(0);
     tcg_gen_extrl_i64_i32(c.u.s32.a, t);
     tcg_temp_free_i64(t);
 
@@ -1649,7 +1649,7 @@ static DisasJumpType op_bct64(DisasContext *s, DisasOps *o)
 
     tcg_gen_subi_i64(regs[r1], regs[r1], 1);
     c.u.s64.a = regs[r1];
-    c.u.s64.b = tcg_const_i64(0);
+    c.u.s64.b = tcg_constant_i64(0);
 
     return help_branch(s, &c, is_imm, imm, o->in2);
 }
-- 
2.34.1



  parent reply	other threads:[~2022-12-11 15:29 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-11 15:27 [PATCH v2 00/27] target/s390x: pc-relative translation blocks Richard Henderson
2022-12-11 15:27 ` [PATCH v2 01/27] target/s390x: Use tcg_constant_* in local contexts Richard Henderson
2022-12-11 15:27 ` Richard Henderson [this message]
2022-12-11 15:43   ` [PATCH v2 02/27] target/s390x: Use tcg_constant_* for DisasCompare Philippe Mathieu-Daudé
2022-12-11 15:27 ` [PATCH v2 03/27] target/s390x: Use tcg_constant_i32 for fpinst_extract_m34 Richard Henderson
2022-12-11 15:44   ` Philippe Mathieu-Daudé
2022-12-11 15:27 ` [PATCH v2 04/27] target/s390x: Use tcg_constant_* in translate_vx.c.inc Richard Henderson
2022-12-11 15:45   ` Philippe Mathieu-Daudé
2022-12-11 15:27 ` [PATCH v2 05/27] tests/tcg/s390x: Add bal.S Richard Henderson
2022-12-11 15:27 ` [PATCH v2 06/27] tests/tcg/s390x: Add sam.S Richard Henderson
2022-12-11 15:27 ` [PATCH v2 07/27] target/s390x: Change help_goto_direct to work on displacements Richard Henderson
2022-12-11 15:47   ` Philippe Mathieu-Daudé
2022-12-11 15:27 ` [PATCH v2 08/27] target/s390x: Introduce gen_psw_addr_disp Richard Henderson
2022-12-11 15:27 ` [PATCH v2 09/27] target/s390x: Remove pc argument to pc_to_link_into Richard Henderson
2022-12-11 15:27 ` [PATCH v2 10/27] target/s390x: Use gen_psw_addr_disp in pc_to_link_info Richard Henderson
2022-12-11 15:27 ` [PATCH v2 11/27] target/s390x: Use gen_psw_addr_disp in save_link_info Richard Henderson
2022-12-11 15:27 ` [PATCH v2 12/27] target/s390x: Use gen_psw_addr_disp in op_sam Richard Henderson
2022-12-11 15:27 ` [PATCH v2 13/27] target/s390x: Use ilen instead in branches Richard Henderson
2022-12-11 15:52   ` Philippe Mathieu-Daudé
2022-12-11 15:27 ` [PATCH v2 14/27] target/s390x: Assert masking of psw.addr in cpu_get_tb_cpu_state Richard Henderson
2022-12-13 17:14   ` Ilya Leoshkevich
2022-12-11 15:27 ` [PATCH v2 15/27] target/s390x: Add disp argument to update_psw_addr Richard Henderson
2022-12-11 15:57   ` Philippe Mathieu-Daudé
2022-12-11 15:27 ` [PATCH v2 16/27] target/s390x: Don't set gbea for user-only Richard Henderson
2022-12-11 15:27 ` [PATCH v2 17/27] target/s390x: Introduce per_enabled Richard Henderson
2022-12-11 15:27 ` [PATCH v2 18/27] target/s390x: Disable conditional branch-to-next for PER Richard Henderson
2022-12-11 15:27 ` [PATCH v2 19/27] target/s390x: Introduce help_goto_indirect Richard Henderson
2022-12-11 15:58   ` Philippe Mathieu-Daudé
2022-12-13 17:15   ` Ilya Leoshkevich
2022-12-11 15:27 ` [PATCH v2 20/27] target/s390x: Split per_branch Richard Henderson
2022-12-11 15:27 ` [PATCH v2 21/27] target/s390x: Simplify help_branch Richard Henderson
2022-12-11 15:27 ` [PATCH v2 22/27] target/s390x: Split per_breaking_event from per_branch_* Richard Henderson
2022-12-11 15:27 ` [PATCH v2 23/27] target/s390x: Remove PER check from use_goto_tb Richard Henderson
2022-12-11 15:27 ` [PATCH v2 24/27] target/s390x: Fix successful-branch PER events Richard Henderson
2022-12-11 15:28 ` [PATCH v2 25/27] tests/tcg/s390x: Add per.S Richard Henderson
2022-12-11 15:28 ` [PATCH v2 26/27] target/s390x: Pass original r2 register to BCR Richard Henderson
2022-12-11 15:28 ` [PATCH v2 27/27] target/s390x: Enable TARGET_TB_PCREL Richard Henderson
2022-12-14 17:22   ` Ilya Leoshkevich

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