From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Dragan Mladjenovic" <Dragan.Mladjenovic@syrmia.com>,
"Milica Lazarevic" <milica.lazarevic@syrmia.com>,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Djordje Todorovic" <djordje.todorovic@syrmia.com>,
"Aurelien Jarno" <aurelien@aurel32.net>,
"Bernhard Beschow" <shentey@gmail.com>
Subject: [PATCH-for-8.0 v2 11/11] hw/mips/malta: Merge common BL code as bl_setup_gt64120_jump_kernel()
Date: Sun, 11 Dec 2022 21:45:33 +0100 [thread overview]
Message-ID: <20221211204533.85359-12-philmd@linaro.org> (raw)
In-Reply-To: <20221211204533.85359-1-philmd@linaro.org>
Merge common code shared between write_bootloader() and
write_bootloader_nanomips() into bl_setup_gt64120_jump_kernel().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/mips/malta.c | 155 +++++++++++++++++-------------------------------
1 file changed, 56 insertions(+), 99 deletions(-)
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 876bc26a7f..9cd59c13e4 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -610,11 +610,64 @@ static void network_init(PCIBus *pci_bus)
}
}
+static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr,
+ uint64_t kernel_entry)
+{
+ /* Bus endianess is always reversed */
+#if TARGET_BIG_ENDIAN
+#define cpu_to_gt32 cpu_to_le32
+#else
+#define cpu_to_gt32 cpu_to_be32
+#endif
+
+ /* setup MEM-to-PCI0 mapping as done by YAMON */
+
+ /* move GT64120 registers from 0x14000000 to 0x1be00000 */
+ bl_gen_write_u32(p, /* GT_ISD */
+ cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68),
+ cpu_to_gt32(0x1be00000 << 3));
+
+ /* setup PCI0 io window to 0x18000000-0x181fffff */
+ bl_gen_write_u32(p, /* GT_PCI0IOLD */
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48),
+ cpu_to_gt32(0x18000000 << 3));
+ bl_gen_write_u32(p, /* GT_PCI0IOHD */
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50),
+ cpu_to_gt32(0x08000000 << 3));
+
+ /* setup PCI0 mem windows */
+ bl_gen_write_u32(p, /* GT_PCI0M0LD */
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),
+ cpu_to_gt32(0x10000000 << 3));
+ bl_gen_write_u32(p, /* GT_PCI0M0HD */
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60),
+ cpu_to_gt32(0x07e00000 << 3));
+ bl_gen_write_u32(p, /* GT_PCI0M1LD */
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80),
+ cpu_to_gt32(0x18200000 << 3));
+ bl_gen_write_u32(p, /* GT_PCI0M1HD */
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88),
+ cpu_to_gt32(0x0bc00000 << 3));
+
+#undef cpu_to_gt32
+
+ bl_gen_jump_kernel(p,
+ true, ENVP_VADDR - 64,
+ /*
+ * If semihosting is used, arguments have already
+ * been passed, so we preserve $a0.
+ */
+ !semihosting_get_argc(), 2,
+ true, ENVP_VADDR,
+ true, ENVP_VADDR + 8,
+ true, loaderparams.ram_low_size,
+ kernel_entry);
+}
+
static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
uint64_t kernel_entry)
{
uint16_t *p;
- void *v;
/* Small bootloader */
p = (uint16_t *)base;
@@ -638,55 +691,7 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
/* to_here: */
-#if TARGET_BIG_ENDIAN
-#define cpu_to_gt32 cpu_to_le32
-#else
-#define cpu_to_gt32 cpu_to_be32
-#endif
- v = p;
-
- /* setup MEM-to-PCI0 mapping as done by YAMON */
-
- /* move GT64120 registers from 0x14000000 to 0x1be00000 */
- bl_gen_write_u32(&v, /* GT_ISD */
- cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68),
- cpu_to_gt32(0x1be00000 << 3));
-
- /* setup PCI0 io window to 0x18000000-0x181fffff */
- bl_gen_write_u32(&v, /* GT_PCI0IOLD */
- cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48),
- cpu_to_gt32(0x18000000 << 3));
- bl_gen_write_u32(&v, /* GT_PCI0IOHD */
- cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50),
- cpu_to_gt32(0x08000000 << 3));
-
- /* setup PCI0 mem windows */
- bl_gen_write_u32(&v, /* GT_PCI0M0LD */
- cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),
- cpu_to_gt32(0x10000000 << 3));
- bl_gen_write_u32(&v, /* GT_PCI0M0HD */
- cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60),
- cpu_to_gt32(0x07e00000 << 3));
- bl_gen_write_u32(&v, /* GT_PCI0M1LD */
- cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80),
- cpu_to_gt32(0x18200000 << 3));
- bl_gen_write_u32(&v, /* GT_PCI0M1HD */
- cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88),
- cpu_to_gt32(0x0bc00000 << 3));
-
-#undef cpu_to_gt32
-
- bl_gen_jump_kernel(&v,
- true, ENVP_VADDR - 64,
- /*
- * If semihosting is used, arguments have already been
- * passed, so we preserve $a0.
- */
- !semihosting_get_argc(), 2,
- true, ENVP_VADDR,
- true, ENVP_VADDR + 8,
- true, loaderparams.ram_low_size,
- kernel_entry);
+ bl_setup_gt64120_jump_kernel((void **)&p, run_addr, kernel_entry);
}
/*
@@ -752,55 +757,8 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr,
*
*/
- /* Bus endianess is always reversed */
-#if TARGET_BIG_ENDIAN
-#define cpu_to_gt32 cpu_to_le32
-#else
-#define cpu_to_gt32 cpu_to_be32
-#endif
v = p;
-
- /* move GT64120 registers from 0x14000000 to 0x1be00000 */
- bl_gen_write_u32(&v, /* GT_ISD */
- cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68),
- cpu_to_gt32(0x1be00000 << 3));
-
- /* setup MEM-to-PCI0 mapping */
- /* setup PCI0 io window to 0x18000000-0x181fffff */
- bl_gen_write_u32(&v, /* GT_PCI0IOLD */
- cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48),
- cpu_to_gt32(0x18000000 << 3));
- bl_gen_write_u32(&v, /* GT_PCI0IOHD */
- cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50),
- cpu_to_gt32(0x08000000 << 3));
- /* setup PCI0 mem windows */
- bl_gen_write_u32(&v, /* GT_PCI0M0LD */
- cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),
- cpu_to_gt32(0x10000000 << 3));
- bl_gen_write_u32(&v, /* GT_PCI0M0HD */
- cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60),
- cpu_to_gt32(0x07e00000 << 3));
-
- bl_gen_write_u32(&v, /* GT_PCI0M1LD */
- cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80),
- cpu_to_gt32(0x18200000 << 3));
- bl_gen_write_u32(&v, /* GT_PCI0M1HD */
- cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88),
- cpu_to_gt32(0x0bc00000 << 3));
-
-#undef cpu_to_gt32
-
- bl_gen_jump_kernel(&v,
- true, ENVP_VADDR - 64,
- /*
- * If semihosting is used, arguments have already been
- * passed, so we preserve $a0.
- */
- !semihosting_get_argc(), 2,
- true, ENVP_VADDR,
- true, ENVP_VADDR + 8,
- true, loaderparams.ram_low_size,
- kernel_entry);
+ bl_setup_gt64120_jump_kernel(&v, run_addr, kernel_entry);
p = v;
/* YAMON subroutines */
@@ -845,7 +803,6 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr,
stl_p(p++, 0x00000000); /* nop */
stl_p(p++, 0x03e00009); /* jalr ra */
stl_p(p++, 0xa1040000); /* sb a0,0(t0) */
-
}
static void G_GNUC_PRINTF(3, 4) prom_set(uint32_t *prom_buf, int index,
--
2.38.1
next prev parent reply other threads:[~2022-12-11 20:47 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-11 20:45 [PATCH-for-8.0 v2 00/11] hw/mips/malta: Generate nanoMIPS bootloader with bootloader generator API Philippe Mathieu-Daudé
2022-12-11 20:45 ` [PATCH-for-8.0 v2 01/11] hw/mips/bootloader: Handle buffers as opaque arrays Philippe Mathieu-Daudé
2022-12-11 20:52 ` Philippe Mathieu-Daudé
2022-12-12 13:46 ` Richard Henderson
2022-12-11 20:45 ` [PATCH-for-8.0 v2 02/11] hw/mips/bootloader: Implement nanoMIPS NOP opcode generator Philippe Mathieu-Daudé
2022-12-11 20:45 ` [PATCH-for-8.0 v2 03/11] hw/mips/bootloader: Implement nanoMIPS SW " Philippe Mathieu-Daudé
2022-12-12 13:50 ` Richard Henderson
2022-12-11 20:45 ` [PATCH-for-8.0 v2 04/11] hw/mips/bootloader: Implement nanoMIPS LI (LUI+ORI) " Philippe Mathieu-Daudé
2022-12-12 13:52 ` Richard Henderson
2022-12-11 20:45 ` [PATCH-for-8.0 v2 05/11] hw/mips/bootloader: Implement nanoMIPS JALRc " Philippe Mathieu-Daudé
2022-12-12 13:55 ` Richard Henderson
2022-12-11 20:45 ` [PATCH-for-8.0 v2 06/11] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (1/5) Philippe Mathieu-Daudé
2022-12-12 14:31 ` Richard Henderson
2022-12-11 20:45 ` [PATCH-for-8.0 v2 07/11] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (2/5) Philippe Mathieu-Daudé
2022-12-12 14:35 ` Richard Henderson
2022-12-11 20:45 ` [PATCH-for-8.0 v2 08/11] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (3/5) Philippe Mathieu-Daudé
2022-12-12 14:37 ` Richard Henderson
2022-12-11 20:45 ` [PATCH-for-8.0 v2 09/11] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (4/5) Philippe Mathieu-Daudé
2022-12-12 14:40 ` Richard Henderson
2022-12-11 20:45 ` [PATCH-for-8.0 v2 10/11] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (5/5) Philippe Mathieu-Daudé
2022-12-12 14:53 ` Richard Henderson
2022-12-11 20:45 ` Philippe Mathieu-Daudé [this message]
2022-12-12 14:58 ` [PATCH-for-8.0 v2 11/11] hw/mips/malta: Merge common BL code as bl_setup_gt64120_jump_kernel() Richard Henderson
2022-12-21 7:07 ` [PATCH-for-8.0 v2 00/11] hw/mips/malta: Generate nanoMIPS bootloader with bootloader generator API Philippe Mathieu-Daudé
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