From: Ilya Leoshkevich <iii@linux.ibm.com>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: thuth@redhat.com
Subject: Re: [PATCH v4 25/27] tcg/s390x: Tighten constraints for 64-bit compare
Date: Tue, 13 Dec 2022 17:25:16 +0100 [thread overview]
Message-ID: <20221213162516.tfiopikzv5ilhgwf@heavy> (raw)
In-Reply-To: <20221209020530.396391-26-richard.henderson@linaro.org>
On Thu, Dec 08, 2022 at 08:05:28PM -0600, Richard Henderson wrote:
> Give 64-bit comparison second operand a signed 33-bit immediate.
> This is the smallest superset of uint32_t and int32_t, as used
> by CLGFI and CGFI respectively. The rest of the 33-bit space
> can be loaded into TCG_TMP0. Drop use of the constant pool.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/s390x/tcg-target-con-set.h | 3 +++
> tcg/s390x/tcg-target.c.inc | 27 ++++++++++++++-------------
> 2 files changed, 17 insertions(+), 13 deletions(-)
<...>
> --- a/tcg/s390x/tcg-target.c.inc
> +++ b/tcg/s390x/tcg-target.c.inc
> @@ -1249,22 +1249,20 @@ static int tgen_cmp2(TCGContext *s, TCGType type, TCGCond c, TCGReg r1,
> tcg_out_insn_RIL(s, op, r1, c2);
> goto exit;
> }
> +
> + /*
> + * Constraints are for a signed 33-bit operand, which is a
> + * convenient superset of this signed/unsigned test.
> + */
> if (c2 == (is_unsigned ? (TCGArg)(uint32_t)c2 : (TCGArg)(int32_t)c2)) {
> op = (is_unsigned ? RIL_CLGFI : RIL_CGFI);
> tcg_out_insn_RIL(s, op, r1, c2);
> goto exit;
> }
>
> - /* Use the constant pool, but not for small constants. */
> - if (maybe_out_small_movi(s, type, TCG_TMP0, c2)) {
> - c2 = TCG_TMP0;
> - /* fall through to reg-reg */
> - } else {
> - op = (is_unsigned ? RIL_CLGRL : RIL_CGRL);
> - tcg_out_insn_RIL(s, op, r1, 0);
> - new_pool_label(s, c2, R_390_PC32DBL, s->code_ptr - 2, 2);
> - goto exit;
> - }
> + /* Load everything else into a register. */
> + tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, c2);
> + c2 = TCG_TMP0;
What does tightening the constraint give us, if we have to handle the
"everything else" case anyway, even for values that match
TCG_CT_CONST_S33?
The example that I have in mind is:
- Comparison: r0_64 s<= -0xffffffffL;
- tcg_target_const_match(-0xffffffffL, TCG_TYPE_I64,
TCG_CT_CONST_S33) == true;
- (long)(int)-0xffffffffL != -0xffffffff;
- So we should end up in the "everything else" branch.
<...>
Best regards,
Ilya
next prev parent reply other threads:[~2022-12-13 16:26 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-09 2:05 [PATCH v4 00/27] tcg/s390x: misc patches Richard Henderson
2022-12-09 2:05 ` [PATCH v4 01/27] tcg/s390x: Use register pair allocation for div and mulu2 Richard Henderson
2022-12-09 2:05 ` [PATCH v4 02/27] tcg/s390x: Remove TCG_REG_TB Richard Henderson
2022-12-09 2:05 ` [PATCH v4 03/27] tcg/s390x: Always set TCG_TARGET_HAS_direct_jump Richard Henderson
2022-12-12 21:51 ` Ilya Leoshkevich
2022-12-09 2:05 ` [PATCH v4 04/27] tcg/s390x: Remove USE_LONG_BRANCHES Richard Henderson
2022-12-12 21:52 ` Ilya Leoshkevich
2022-12-09 2:05 ` [PATCH v4 05/27] tcg/s390x: Check for long-displacement facility at startup Richard Henderson
2022-12-12 21:54 ` Ilya Leoshkevich
2022-12-09 2:05 ` [PATCH v4 06/27] tcg/s390x: Check for extended-immediate " Richard Henderson
2022-12-12 22:17 ` Ilya Leoshkevich
2022-12-09 2:05 ` [PATCH v4 07/27] tcg/s390x: Check for general-instruction-extension " Richard Henderson
2022-12-12 22:21 ` Ilya Leoshkevich
2022-12-09 2:05 ` [PATCH v4 08/27] tcg/s390x: Check for load-on-condition " Richard Henderson
2022-12-12 22:26 ` Ilya Leoshkevich
2022-12-09 2:05 ` [PATCH v4 09/27] tcg/s390x: Remove FAST_BCR_SER facility check Richard Henderson
2022-12-12 22:08 ` Philippe Mathieu-Daudé
2022-12-09 2:05 ` [PATCH v4 10/27] tcg/s390x: Remove DISTINCT_OPERANDS " Richard Henderson
2022-12-12 22:29 ` Ilya Leoshkevich
2022-12-09 2:05 ` [PATCH v4 11/27] tcg/s390x: Use LARL+AGHI for odd addresses Richard Henderson
2022-12-09 2:05 ` [PATCH v4 12/27] tcg/s390x: Distinguish RRF-a and RRF-c formats Richard Henderson
2022-12-09 2:05 ` [PATCH v4 13/27] tcg/s390x: Distinguish RIE formats Richard Henderson
2022-12-09 2:05 ` [PATCH v4 14/27] tcg/s390x: Support MIE2 multiply single instructions Richard Henderson
2022-12-09 2:05 ` [PATCH v4 15/27] tcg/s390x: Support MIE2 MGRK instruction Richard Henderson
2022-12-09 2:05 ` [PATCH v4 16/27] tcg/s390x: Issue XILF directly for xor_i32 Richard Henderson
2022-12-12 22:30 ` Ilya Leoshkevich
2022-12-09 2:05 ` [PATCH v4 17/27] tcg/s390x: Tighten constraints for or_i64 and xor_i64 Richard Henderson
2022-12-12 22:41 ` Ilya Leoshkevich
2022-12-09 2:05 ` [PATCH v4 18/27] tcg/s390x: Tighten constraints for and_i64 Richard Henderson
2022-12-12 22:57 ` Ilya Leoshkevich
2022-12-09 2:05 ` [PATCH v4 19/27] tcg/s390x: Support MIE3 logical operations Richard Henderson
2022-12-09 2:05 ` [PATCH v4 20/27] tcg/s390x: Create tgen_cmp2 to simplify movcond Richard Henderson
2022-12-09 2:05 ` [PATCH v4 21/27] tcg/s390x: Generalize movcond implementation Richard Henderson
2022-12-09 2:05 ` [PATCH v4 22/27] tcg/s390x: Support SELGR instruction in movcond Richard Henderson
2022-12-09 2:05 ` [PATCH v4 23/27] tcg/s390x: Use tgen_movcond_int in tgen_clz Richard Henderson
2022-12-09 2:05 ` [PATCH v4 24/27] tcg/s390x: Implement ctpop operation Richard Henderson
2022-12-09 2:05 ` [PATCH v4 25/27] tcg/s390x: Tighten constraints for 64-bit compare Richard Henderson
2022-12-13 16:25 ` Ilya Leoshkevich [this message]
2022-12-13 16:43 ` Richard Henderson
2022-12-13 17:01 ` Ilya Leoshkevich
2022-12-09 2:05 ` [PATCH v4 26/27] tcg/s390x: Cleanup tcg_out_movi Richard Henderson
2022-12-13 16:29 ` Ilya Leoshkevich
2022-12-09 2:05 ` [PATCH v4 27/27] tcg/s390x: Avoid the constant pool in tcg_out_movi Richard Henderson
2022-12-13 16:31 ` Ilya Leoshkevich
2022-12-13 16:35 ` [PATCH v4 00/27] tcg/s390x: misc patches Ilya Leoshkevich
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