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Tsirkin" To: Bernhard Beschow Cc: Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , qemu-devel@nongnu.org, John G Johnson , Peter Maydell , Huacai Chen , Jiaxun Yang , Aurelien Jarno , Paolo Bonzini , Marcel Apfelbaum , =?iso-8859-1?Q?Herv=E9?= Poussineau , Elena Ufimtseva , Eduardo Habkost , Jagannathan Raman , Richard Henderson , qemu-ppc@nongnu.org, qemu-arm@nongnu.org Subject: Re: [PATCH v2 0/3] Decouple INTx-to-LNKx routing from south bridges Message-ID: <20221218080511-mutt-send-email-mst@kernel.org> References: <20221120150550.63059-1-shentey@gmail.com> <17a7d714-8a1e-8a17-f657-2172060d02e5@linaro.org> <3F5A5F52-5815-4CB2-9DE8-894D59B0EB8C@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <3F5A5F52-5815-4CB2-9DE8-894D59B0EB8C@gmail.com> Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Sun, Dec 18, 2022 at 10:21:49AM +0000, Bernhard Beschow wrote: > > > Am 9. Dezember 2022 15:23:59 UTC schrieb "Philippe Mathieu-Daudé" : > >On 20/11/22 16:05, Bernhard Beschow wrote: > >> v1: > >> === > >> > >> During my PIIX consolidation work [1] I've noticed that both PIIX models have > >> quite different pci_slot_get_pirq() implementations. These functions seem to > >> map PCI INTx pins to input pins of a programmable interrupt router which is > >> AFAIU board-specific. IOW, board-specific assumptions are baked into the device > >> models which prevent e.g. the whole PIIX4 south bridge to be reusable in the PC > >> machine. > >> > >> This series first factors out pci_bus_map_irqs() from pci_bus_irqs() which > >> then allowes for moving the two board-specific PIIX pci_slot_get_pirq() > >> funtions into their respective boards. With these changes, the PIIX4 south > >> bridge could eventually become an alternative to the PIIX3-Frankenstein > >> solution in the PC machine. > > > >Series: > >Reviewed-by: Philippe Mathieu-Daudé > > Ping > > Who will pull this? I'll merge this, thanks!