From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com,
"Frédéric Pétrot" <frederic.petrot@univ-grenoble-alpes.fr>,
"Alistair Francis" <alistair.francis@wdc.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PULL 16/45] hw/intc: sifive_plic: Renumber the S irqs for numa support
Date: Mon, 19 Dec 2022 12:16:34 +1000 [thread overview]
Message-ID: <20221219021703.20473-17-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20221219021703.20473-1-alistair.francis@opensource.wdc.com>
From: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Commit 40244040a7a changed the way the S irqs are numbered. This breaks when
using numa configuration, e.g.:
./qemu-system-riscv64 -nographic -machine virt,dumpdtb=numa-tree.dtb \
-m 2G -smp cpus=16 \
-object memory-backend-ram,id=mem0,size=512M \
-object memory-backend-ram,id=mem1,size=512M \
-object memory-backend-ram,id=mem2,size=512M \
-object memory-backend-ram,id=mem3,size=512M \
-numa node,cpus=0-3,memdev=mem0,nodeid=0 \
-numa node,cpus=4-7,memdev=mem1,nodeid=1 \
-numa node,cpus=8-11,memdev=mem2,nodeid=2 \
-numa node,cpus=12-15,memdev=mem3,nodeid=3
leads to:
Unexpected error in object_property_find_err() at ../qom/object.c:1304:
qemu-system-riscv64: Property 'riscv.sifive.plic.unnamed-gpio-out[8]' not
found
This patch makes the nubering of the S irqs identical to what it was before.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Message-Id: <20221114135122.1668703-1-frederic.petrot@univ-grenoble-alpes.fr>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/intc/sifive_plic.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index c2dfacf028..b4949bef97 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -476,11 +476,11 @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
CPUState *cpu = qemu_get_cpu(cpu_num);
if (plic->addr_config[i].mode == PLICMode_M) {
- qdev_connect_gpio_out(dev, num_harts - plic->hartid_base + cpu_num,
+ qdev_connect_gpio_out(dev, cpu_num - hartid_base + num_harts,
qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
}
if (plic->addr_config[i].mode == PLICMode_S) {
- qdev_connect_gpio_out(dev, cpu_num,
+ qdev_connect_gpio_out(dev, cpu_num - hartid_base,
qdev_get_gpio_in(DEVICE(cpu), IRQ_S_EXT));
}
}
--
2.38.1
next prev parent reply other threads:[~2022-12-19 2:19 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-19 2:16 [PULL 00/45] riscv-to-apply queue Alistair Francis
2022-12-19 2:16 ` [PULL 01/45] target/riscv: Fix PMP propagation for tlb Alistair Francis
2022-12-19 2:16 ` [PULL 02/45] hw/registerfields: add `FIELDx_1CLEAR()` macro Alistair Francis
2022-12-19 2:16 ` [PULL 03/45] hw/ssi/ibex_spi: implement `FIELD32_1CLEAR` macro Alistair Francis
2022-12-19 2:16 ` [PULL 04/45] tcg/riscv: Fix range matched by TCG_CT_CONST_M12 Alistair Francis
2022-12-19 2:16 ` [PULL 05/45] tcg/riscv: Fix reg overlap case in tcg_out_addsub2 Alistair Francis
2022-12-19 2:16 ` [PULL 06/45] tcg/riscv: Fix base register for user-only qemu_ld/st Alistair Francis
2022-12-19 2:16 ` [PULL 07/45] hw/riscv/opentitan: bump opentitan Alistair Francis
2022-12-19 2:16 ` [PULL 08/45] hw/riscv/opentitan: add aon_timer base unimpl Alistair Francis
2022-12-19 2:16 ` [PULL 09/45] target/riscv: Add smstateen support Alistair Francis
2022-12-19 2:16 ` [PULL 10/45] target/riscv: smstateen check for h/s/envcfg Alistair Francis
2022-12-19 2:16 ` [PULL 11/45] target/riscv: generate virtual instruction exception Alistair Francis
2022-12-19 2:16 ` [PULL 12/45] target/riscv: Add itrigger support when icount is not enabled Alistair Francis
2022-12-19 2:16 ` [PULL 13/45] target/riscv: Add itrigger support when icount is enabled Alistair Francis
2022-12-19 2:16 ` [PULL 14/45] target/riscv: Enable native debug itrigger Alistair Francis
2022-12-19 2:16 ` [PULL 15/45] target/riscv: Add itrigger_enabled field to CPURISCVState Alistair Francis
2022-12-19 2:16 ` Alistair Francis [this message]
2022-12-19 2:16 ` [PULL 17/45] target/riscv: Typo fix in sstc() predicate Alistair Francis
2022-12-19 2:16 ` [PULL 18/45] hw/riscv: virt: Remove the redundant ipi-id property Alistair Francis
2022-12-19 2:16 ` [PULL 19/45] target/riscv: support cache-related PMU events in virtual mode Alistair Francis
2022-12-19 2:16 ` [PULL 20/45] target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state() Alistair Francis
2022-12-19 2:16 ` [PULL 21/45] hw/misc: pfsoc: add fabric clocks to ioscb Alistair Francis
2022-12-19 2:16 ` [PULL 22/45] hw/riscv: pfsoc: add missing FICs as unimplemented Alistair Francis
2022-12-19 2:16 ` [PULL 23/45] hw/{misc, riscv}: pfsoc: add system controller " Alistair Francis
2022-12-19 2:16 ` [PULL 24/45] hw/intc: sifive_plic: fix out-of-bound access of source_priority array Alistair Francis
2022-12-19 2:16 ` [PULL 25/45] target/riscv: Fix mret exception cause when no pmp rule is configured Alistair Francis
2022-12-19 2:16 ` [PULL 26/45] target/riscv: Set pc_succ_insn for !rvc illegal insn Alistair Francis
2022-12-19 2:16 ` [PULL 27/45] target/riscv: Simplify helper_sret() a little bit Alistair Francis
2022-12-19 2:16 ` [PULL 28/45] target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+ Alistair Francis
2022-12-19 2:16 ` [PULL 29/45] RISC-V: Add Zawrs ISA extension support Alistair Francis
2022-12-19 2:16 ` [PULL 30/45] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Alistair Francis
2022-12-19 2:16 ` [PULL 31/45] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers Alistair Francis
2022-12-19 2:16 ` [PULL 32/45] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC Alistair Francis
2022-12-19 2:16 ` [PULL 33/45] hw/riscv: Sort machines Kconfig options in alphabetical order Alistair Francis
2022-12-19 2:16 ` [PULL 34/45] hw/riscv: spike: Remove misleading comments Alistair Francis
2022-12-19 2:16 ` [PULL 35/45] hw/intc: sifive_plic: Drop PLICMode_H Alistair Francis
2022-12-19 2:16 ` [PULL 36/45] hw/intc: sifive_plic: Improve robustness of the PLIC config parser Alistair Francis
2022-12-19 2:16 ` [PULL 37/45] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize() Alistair Francis
2022-12-19 2:16 ` [PULL 38/45] hw/intc: sifive_plic: Update "num-sources" property default value Alistair Francis
2022-12-19 2:16 ` [PULL 39/45] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC Alistair Francis
2022-12-19 2:16 ` [PULL 40/45] hw/riscv: sifive_e: " Alistair Francis
2022-12-19 2:16 ` [PULL 41/45] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev" Alistair Francis
2022-12-19 2:17 ` [PULL 42/45] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb Alistair Francis
2022-12-19 2:17 ` [PULL 43/45] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0 Alistair Francis
2022-12-19 2:17 ` [PULL 44/45] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization Alistair Francis
2022-12-19 2:17 ` [PULL 45/45] hw/intc: sifive_plic: Fix the pending register range check Alistair Francis
2022-12-19 15:11 ` [PULL 00/45] riscv-to-apply queue Peter Maydell
2022-12-19 23:28 ` Alistair Francis
2022-12-20 15:32 ` Peter Maydell
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