From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Bin Meng <bmeng@tinylab.org>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 27/45] target/riscv: Simplify helper_sret() a little bit
Date: Mon, 19 Dec 2022 12:16:45 +1000 [thread overview]
Message-ID: <20221219021703.20473-28-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20221219021703.20473-1-alistair.francis@opensource.wdc.com>
From: Bin Meng <bmeng@tinylab.org>
There are 2 paths in helper_sret() and the same mstatus update codes
are replicated. Extract the common parts to simplify it a little bit.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221207090037.281452-1-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/op_helper.c | 20 ++++++--------------
1 file changed, 6 insertions(+), 14 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index d7af7f056b..a047d38152 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -149,21 +149,21 @@ target_ulong helper_sret(CPURISCVState *env)
}
mstatus = env->mstatus;
+ prev_priv = get_field(mstatus, MSTATUS_SPP);
+ mstatus = set_field(mstatus, MSTATUS_SIE,
+ get_field(mstatus, MSTATUS_SPIE));
+ mstatus = set_field(mstatus, MSTATUS_SPIE, 1);
+ mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
+ env->mstatus = mstatus;
if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
/* We support Hypervisor extensions and virtulisation is disabled */
target_ulong hstatus = env->hstatus;
- prev_priv = get_field(mstatus, MSTATUS_SPP);
prev_virt = get_field(hstatus, HSTATUS_SPV);
hstatus = set_field(hstatus, HSTATUS_SPV, 0);
- mstatus = set_field(mstatus, MSTATUS_SPP, 0);
- mstatus = set_field(mstatus, SSTATUS_SIE,
- get_field(mstatus, SSTATUS_SPIE));
- mstatus = set_field(mstatus, SSTATUS_SPIE, 1);
- env->mstatus = mstatus;
env->hstatus = hstatus;
if (prev_virt) {
@@ -171,14 +171,6 @@ target_ulong helper_sret(CPURISCVState *env)
}
riscv_cpu_set_virt_enabled(env, prev_virt);
- } else {
- prev_priv = get_field(mstatus, MSTATUS_SPP);
-
- mstatus = set_field(mstatus, MSTATUS_SIE,
- get_field(mstatus, MSTATUS_SPIE));
- mstatus = set_field(mstatus, MSTATUS_SPIE, 1);
- mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
- env->mstatus = mstatus;
}
riscv_cpu_set_mode(env, prev_priv);
--
2.38.1
next prev parent reply other threads:[~2022-12-19 2:18 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-19 2:16 [PULL 00/45] riscv-to-apply queue Alistair Francis
2022-12-19 2:16 ` [PULL 01/45] target/riscv: Fix PMP propagation for tlb Alistair Francis
2022-12-19 2:16 ` [PULL 02/45] hw/registerfields: add `FIELDx_1CLEAR()` macro Alistair Francis
2022-12-19 2:16 ` [PULL 03/45] hw/ssi/ibex_spi: implement `FIELD32_1CLEAR` macro Alistair Francis
2022-12-19 2:16 ` [PULL 04/45] tcg/riscv: Fix range matched by TCG_CT_CONST_M12 Alistair Francis
2022-12-19 2:16 ` [PULL 05/45] tcg/riscv: Fix reg overlap case in tcg_out_addsub2 Alistair Francis
2022-12-19 2:16 ` [PULL 06/45] tcg/riscv: Fix base register for user-only qemu_ld/st Alistair Francis
2022-12-19 2:16 ` [PULL 07/45] hw/riscv/opentitan: bump opentitan Alistair Francis
2022-12-19 2:16 ` [PULL 08/45] hw/riscv/opentitan: add aon_timer base unimpl Alistair Francis
2022-12-19 2:16 ` [PULL 09/45] target/riscv: Add smstateen support Alistair Francis
2022-12-19 2:16 ` [PULL 10/45] target/riscv: smstateen check for h/s/envcfg Alistair Francis
2022-12-19 2:16 ` [PULL 11/45] target/riscv: generate virtual instruction exception Alistair Francis
2022-12-19 2:16 ` [PULL 12/45] target/riscv: Add itrigger support when icount is not enabled Alistair Francis
2022-12-19 2:16 ` [PULL 13/45] target/riscv: Add itrigger support when icount is enabled Alistair Francis
2022-12-19 2:16 ` [PULL 14/45] target/riscv: Enable native debug itrigger Alistair Francis
2022-12-19 2:16 ` [PULL 15/45] target/riscv: Add itrigger_enabled field to CPURISCVState Alistair Francis
2022-12-19 2:16 ` [PULL 16/45] hw/intc: sifive_plic: Renumber the S irqs for numa support Alistair Francis
2022-12-19 2:16 ` [PULL 17/45] target/riscv: Typo fix in sstc() predicate Alistair Francis
2022-12-19 2:16 ` [PULL 18/45] hw/riscv: virt: Remove the redundant ipi-id property Alistair Francis
2022-12-19 2:16 ` [PULL 19/45] target/riscv: support cache-related PMU events in virtual mode Alistair Francis
2022-12-19 2:16 ` [PULL 20/45] target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state() Alistair Francis
2022-12-19 2:16 ` [PULL 21/45] hw/misc: pfsoc: add fabric clocks to ioscb Alistair Francis
2022-12-19 2:16 ` [PULL 22/45] hw/riscv: pfsoc: add missing FICs as unimplemented Alistair Francis
2022-12-19 2:16 ` [PULL 23/45] hw/{misc, riscv}: pfsoc: add system controller " Alistair Francis
2022-12-19 2:16 ` [PULL 24/45] hw/intc: sifive_plic: fix out-of-bound access of source_priority array Alistair Francis
2022-12-19 2:16 ` [PULL 25/45] target/riscv: Fix mret exception cause when no pmp rule is configured Alistair Francis
2022-12-19 2:16 ` [PULL 26/45] target/riscv: Set pc_succ_insn for !rvc illegal insn Alistair Francis
2022-12-19 2:16 ` Alistair Francis [this message]
2022-12-19 2:16 ` [PULL 28/45] target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+ Alistair Francis
2022-12-19 2:16 ` [PULL 29/45] RISC-V: Add Zawrs ISA extension support Alistair Francis
2022-12-19 2:16 ` [PULL 30/45] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Alistair Francis
2022-12-19 2:16 ` [PULL 31/45] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers Alistair Francis
2022-12-19 2:16 ` [PULL 32/45] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC Alistair Francis
2022-12-19 2:16 ` [PULL 33/45] hw/riscv: Sort machines Kconfig options in alphabetical order Alistair Francis
2022-12-19 2:16 ` [PULL 34/45] hw/riscv: spike: Remove misleading comments Alistair Francis
2022-12-19 2:16 ` [PULL 35/45] hw/intc: sifive_plic: Drop PLICMode_H Alistair Francis
2022-12-19 2:16 ` [PULL 36/45] hw/intc: sifive_plic: Improve robustness of the PLIC config parser Alistair Francis
2022-12-19 2:16 ` [PULL 37/45] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize() Alistair Francis
2022-12-19 2:16 ` [PULL 38/45] hw/intc: sifive_plic: Update "num-sources" property default value Alistair Francis
2022-12-19 2:16 ` [PULL 39/45] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC Alistair Francis
2022-12-19 2:16 ` [PULL 40/45] hw/riscv: sifive_e: " Alistair Francis
2022-12-19 2:16 ` [PULL 41/45] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev" Alistair Francis
2022-12-19 2:17 ` [PULL 42/45] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb Alistair Francis
2022-12-19 2:17 ` [PULL 43/45] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0 Alistair Francis
2022-12-19 2:17 ` [PULL 44/45] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization Alistair Francis
2022-12-19 2:17 ` [PULL 45/45] hw/intc: sifive_plic: Fix the pending register range check Alistair Francis
2022-12-19 15:11 ` [PULL 00/45] riscv-to-apply queue Peter Maydell
2022-12-19 23:28 ` Alistair Francis
2022-12-20 15:32 ` Peter Maydell
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