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charset=UTF-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=345d64987=alistair.francis@opensource.wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Bin Meng The realize() callback has an errp for us to propagate the error up. While we are here, correct the wrong multi-line comment format. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20221211030829.802437-8-bmeng@tinylab.org> Signed-off-by: Alistair Francis --- hw/intc/sifive_plic.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index c9af94a888..9cb4c6d6d4 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -379,7 +379,8 @@ static void sifive_plic_realize(DeviceState *dev, Err= or **errp) s->m_external_irqs =3D g_malloc(sizeof(qemu_irq) * s->num_harts); qdev_init_gpio_out(dev, s->m_external_irqs, s->num_harts); =20 - /* We can't allow the supervisor to control SEIP as this would allow= the + /* + * We can't allow the supervisor to control SEIP as this would allow= the * supervisor to clear a pending external interrupt which will resul= t in * lost a interrupt in the case a PLIC is attached. The SEIP bit mus= t be * hardware controlled when a PLIC is attached. @@ -387,8 +388,8 @@ static void sifive_plic_realize(DeviceState *dev, Err= or **errp) for (i =3D 0; i < s->num_harts; i++) { RISCVCPU *cpu =3D RISCV_CPU(qemu_get_cpu(s->hartid_base + i)); if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) { - error_report("SEIP already claimed"); - exit(1); + error_setg(errp, "SEIP already claimed"); + return; } } =20 --=20 2.38.1