qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Bin Meng <bmeng@tinylab.org>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 42/45] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb
Date: Mon, 19 Dec 2022 12:17:00 +1000	[thread overview]
Message-ID: <20221219021703.20473-43-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20221219021703.20473-1-alistair.francis@opensource.wdc.com>

From: Bin Meng <bmeng@tinylab.org>

Commit 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to virt machine")
changed the value of VIRT_IRQCHIP_NUM_SOURCES from 127 to 53, which
is VIRTIO_NDEV and also used as the value of "riscv,ndev" property
in the dtb. Unfortunately this is wrong as VIRT_IRQCHIP_NUM_SOURCES
should include interrupt source 0 but "riscv,ndev" does not.

While we are here, we also fix the comments of platform bus irq range
which is now "64 to 96", but should be "64 to 95", introduced since
commit 1832b7cb3f64 ("hw/riscv: virt: Create a platform bus").

Fixes: 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to virt machine")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221211030829.802437-13-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/virt.h | 5 ++---
 hw/riscv/virt.c         | 3 ++-
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 62513e075c..e1ce0048af 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -87,14 +87,13 @@ enum {
     VIRTIO_IRQ = 1, /* 1 to 8 */
     VIRTIO_COUNT = 8,
     PCIE_IRQ = 0x20, /* 32 to 35 */
-    VIRT_PLATFORM_BUS_IRQ = 64, /* 64 to 96 */
-    VIRTIO_NDEV = 96 /* Arbitrary maximum number of interrupts */
+    VIRT_PLATFORM_BUS_IRQ = 64, /* 64 to 95 */
 };
 
 #define VIRT_PLATFORM_BUS_NUM_IRQS 32
 
 #define VIRT_IRQCHIP_NUM_MSIS 255
-#define VIRT_IRQCHIP_NUM_SOURCES VIRTIO_NDEV
+#define VIRT_IRQCHIP_NUM_SOURCES 96
 #define VIRT_IRQCHIP_NUM_PRIO_BITS 3
 #define VIRT_IRQCHIP_MAX_GUESTS_BITS 3
 #define VIRT_IRQCHIP_MAX_GUESTS ((1U << VIRT_IRQCHIP_MAX_GUESTS_BITS) - 1U)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 6cf9355b99..94ff2a1584 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -468,7 +468,8 @@ static void create_fdt_socket_plic(RISCVVirtState *s,
         plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
     qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg",
         0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size);
-    qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", VIRTIO_NDEV);
+    qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev",
+                          VIRT_IRQCHIP_NUM_SOURCES - 1);
     riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket);
     qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle",
         plic_phandles[socket]);
-- 
2.38.1



  parent reply	other threads:[~2022-12-19  2:31 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-19  2:16 [PULL 00/45] riscv-to-apply queue Alistair Francis
2022-12-19  2:16 ` [PULL 01/45] target/riscv: Fix PMP propagation for tlb Alistair Francis
2022-12-19  2:16 ` [PULL 02/45] hw/registerfields: add `FIELDx_1CLEAR()` macro Alistair Francis
2022-12-19  2:16 ` [PULL 03/45] hw/ssi/ibex_spi: implement `FIELD32_1CLEAR` macro Alistair Francis
2022-12-19  2:16 ` [PULL 04/45] tcg/riscv: Fix range matched by TCG_CT_CONST_M12 Alistair Francis
2022-12-19  2:16 ` [PULL 05/45] tcg/riscv: Fix reg overlap case in tcg_out_addsub2 Alistair Francis
2022-12-19  2:16 ` [PULL 06/45] tcg/riscv: Fix base register for user-only qemu_ld/st Alistair Francis
2022-12-19  2:16 ` [PULL 07/45] hw/riscv/opentitan: bump opentitan Alistair Francis
2022-12-19  2:16 ` [PULL 08/45] hw/riscv/opentitan: add aon_timer base unimpl Alistair Francis
2022-12-19  2:16 ` [PULL 09/45] target/riscv: Add smstateen support Alistair Francis
2022-12-19  2:16 ` [PULL 10/45] target/riscv: smstateen check for h/s/envcfg Alistair Francis
2022-12-19  2:16 ` [PULL 11/45] target/riscv: generate virtual instruction exception Alistair Francis
2022-12-19  2:16 ` [PULL 12/45] target/riscv: Add itrigger support when icount is not enabled Alistair Francis
2022-12-19  2:16 ` [PULL 13/45] target/riscv: Add itrigger support when icount is enabled Alistair Francis
2022-12-19  2:16 ` [PULL 14/45] target/riscv: Enable native debug itrigger Alistair Francis
2022-12-19  2:16 ` [PULL 15/45] target/riscv: Add itrigger_enabled field to CPURISCVState Alistair Francis
2022-12-19  2:16 ` [PULL 16/45] hw/intc: sifive_plic: Renumber the S irqs for numa support Alistair Francis
2022-12-19  2:16 ` [PULL 17/45] target/riscv: Typo fix in sstc() predicate Alistair Francis
2022-12-19  2:16 ` [PULL 18/45] hw/riscv: virt: Remove the redundant ipi-id property Alistair Francis
2022-12-19  2:16 ` [PULL 19/45] target/riscv: support cache-related PMU events in virtual mode Alistair Francis
2022-12-19  2:16 ` [PULL 20/45] target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state() Alistair Francis
2022-12-19  2:16 ` [PULL 21/45] hw/misc: pfsoc: add fabric clocks to ioscb Alistair Francis
2022-12-19  2:16 ` [PULL 22/45] hw/riscv: pfsoc: add missing FICs as unimplemented Alistair Francis
2022-12-19  2:16 ` [PULL 23/45] hw/{misc, riscv}: pfsoc: add system controller " Alistair Francis
2022-12-19  2:16 ` [PULL 24/45] hw/intc: sifive_plic: fix out-of-bound access of source_priority array Alistair Francis
2022-12-19  2:16 ` [PULL 25/45] target/riscv: Fix mret exception cause when no pmp rule is configured Alistair Francis
2022-12-19  2:16 ` [PULL 26/45] target/riscv: Set pc_succ_insn for !rvc illegal insn Alistair Francis
2022-12-19  2:16 ` [PULL 27/45] target/riscv: Simplify helper_sret() a little bit Alistair Francis
2022-12-19  2:16 ` [PULL 28/45] target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+ Alistair Francis
2022-12-19  2:16 ` [PULL 29/45] RISC-V: Add Zawrs ISA extension support Alistair Francis
2022-12-19  2:16 ` [PULL 30/45] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Alistair Francis
2022-12-19  2:16 ` [PULL 31/45] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers Alistair Francis
2022-12-19  2:16 ` [PULL 32/45] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC Alistair Francis
2022-12-19  2:16 ` [PULL 33/45] hw/riscv: Sort machines Kconfig options in alphabetical order Alistair Francis
2022-12-19  2:16 ` [PULL 34/45] hw/riscv: spike: Remove misleading comments Alistair Francis
2022-12-19  2:16 ` [PULL 35/45] hw/intc: sifive_plic: Drop PLICMode_H Alistair Francis
2022-12-19  2:16 ` [PULL 36/45] hw/intc: sifive_plic: Improve robustness of the PLIC config parser Alistair Francis
2022-12-19  2:16 ` [PULL 37/45] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize() Alistair Francis
2022-12-19  2:16 ` [PULL 38/45] hw/intc: sifive_plic: Update "num-sources" property default value Alistair Francis
2022-12-19  2:16 ` [PULL 39/45] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC Alistair Francis
2022-12-19  2:16 ` [PULL 40/45] hw/riscv: sifive_e: " Alistair Francis
2022-12-19  2:16 ` [PULL 41/45] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev" Alistair Francis
2022-12-19  2:17 ` Alistair Francis [this message]
2022-12-19  2:17 ` [PULL 43/45] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0 Alistair Francis
2022-12-19  2:17 ` [PULL 44/45] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization Alistair Francis
2022-12-19  2:17 ` [PULL 45/45] hw/intc: sifive_plic: Fix the pending register range check Alistair Francis
2022-12-19 15:11 ` [PULL 00/45] riscv-to-apply queue Peter Maydell
2022-12-19 23:28   ` Alistair Francis
2022-12-20 15:32     ` Peter Maydell

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20221219021703.20473-43-alistair.francis@opensource.wdc.com \
    --to=alistair.francis@opensource.wdc.com \
    --cc=alistair.francis@wdc.com \
    --cc=alistair23@gmail.com \
    --cc=bmeng@tinylab.org \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).