From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com,
Richard Henderson <richard.henderson@linaro.org>,
LIU Zhiwei <zhiwei_liu@linux.alibaba.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 04/45] tcg/riscv: Fix range matched by TCG_CT_CONST_M12
Date: Mon, 19 Dec 2022 12:16:22 +1000 [thread overview]
Message-ID: <20221219021703.20473-5-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20221219021703.20473-1-alistair.francis@opensource.wdc.com>
From: Richard Henderson <richard.henderson@linaro.org>
We were matching a signed 13-bit range, not a 12-bit range.
Expand the commentary within the function and be explicit
about all of the ranges.
Reported-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221022095821.2441874-1-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
tcg/riscv/tcg-target.c.inc | 19 ++++++++++++++++---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 81a83e45b1..191197853f 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -154,13 +154,26 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
return 1;
}
- if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) {
+ /*
+ * Sign extended from 12 bits: [-0x800, 0x7ff].
+ * Used for most arithmetic, as this is the isa field.
+ */
+ if ((ct & TCG_CT_CONST_S12) && val >= -0x800 && val <= 0x7ff) {
return 1;
}
- if ((ct & TCG_CT_CONST_N12) && -val == sextreg(-val, 0, 12)) {
+ /*
+ * Sign extended from 12 bits, negated: [-0x7ff, 0x800].
+ * Used for subtraction, where a constant must be handled by ADDI.
+ */
+ if ((ct & TCG_CT_CONST_N12) && val >= -0x7ff && val <= 0x800) {
return 1;
}
- if ((ct & TCG_CT_CONST_M12) && val >= -0xfff && val <= 0xfff) {
+ /*
+ * Sign extended from 12 bits, +/- matching: [-0x7ff, 0x7ff].
+ * Used by addsub2, which may need the negative operation,
+ * and requires the modified constant to be representable.
+ */
+ if ((ct & TCG_CT_CONST_M12) && val >= -0x7ff && val <= 0x7ff) {
return 1;
}
return 0;
--
2.38.1
next prev parent reply other threads:[~2022-12-19 2:20 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-19 2:16 [PULL 00/45] riscv-to-apply queue Alistair Francis
2022-12-19 2:16 ` [PULL 01/45] target/riscv: Fix PMP propagation for tlb Alistair Francis
2022-12-19 2:16 ` [PULL 02/45] hw/registerfields: add `FIELDx_1CLEAR()` macro Alistair Francis
2022-12-19 2:16 ` [PULL 03/45] hw/ssi/ibex_spi: implement `FIELD32_1CLEAR` macro Alistair Francis
2022-12-19 2:16 ` Alistair Francis [this message]
2022-12-19 2:16 ` [PULL 05/45] tcg/riscv: Fix reg overlap case in tcg_out_addsub2 Alistair Francis
2022-12-19 2:16 ` [PULL 06/45] tcg/riscv: Fix base register for user-only qemu_ld/st Alistair Francis
2022-12-19 2:16 ` [PULL 07/45] hw/riscv/opentitan: bump opentitan Alistair Francis
2022-12-19 2:16 ` [PULL 08/45] hw/riscv/opentitan: add aon_timer base unimpl Alistair Francis
2022-12-19 2:16 ` [PULL 09/45] target/riscv: Add smstateen support Alistair Francis
2022-12-19 2:16 ` [PULL 10/45] target/riscv: smstateen check for h/s/envcfg Alistair Francis
2022-12-19 2:16 ` [PULL 11/45] target/riscv: generate virtual instruction exception Alistair Francis
2022-12-19 2:16 ` [PULL 12/45] target/riscv: Add itrigger support when icount is not enabled Alistair Francis
2022-12-19 2:16 ` [PULL 13/45] target/riscv: Add itrigger support when icount is enabled Alistair Francis
2022-12-19 2:16 ` [PULL 14/45] target/riscv: Enable native debug itrigger Alistair Francis
2022-12-19 2:16 ` [PULL 15/45] target/riscv: Add itrigger_enabled field to CPURISCVState Alistair Francis
2022-12-19 2:16 ` [PULL 16/45] hw/intc: sifive_plic: Renumber the S irqs for numa support Alistair Francis
2022-12-19 2:16 ` [PULL 17/45] target/riscv: Typo fix in sstc() predicate Alistair Francis
2022-12-19 2:16 ` [PULL 18/45] hw/riscv: virt: Remove the redundant ipi-id property Alistair Francis
2022-12-19 2:16 ` [PULL 19/45] target/riscv: support cache-related PMU events in virtual mode Alistair Francis
2022-12-19 2:16 ` [PULL 20/45] target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state() Alistair Francis
2022-12-19 2:16 ` [PULL 21/45] hw/misc: pfsoc: add fabric clocks to ioscb Alistair Francis
2022-12-19 2:16 ` [PULL 22/45] hw/riscv: pfsoc: add missing FICs as unimplemented Alistair Francis
2022-12-19 2:16 ` [PULL 23/45] hw/{misc, riscv}: pfsoc: add system controller " Alistair Francis
2022-12-19 2:16 ` [PULL 24/45] hw/intc: sifive_plic: fix out-of-bound access of source_priority array Alistair Francis
2022-12-19 2:16 ` [PULL 25/45] target/riscv: Fix mret exception cause when no pmp rule is configured Alistair Francis
2022-12-19 2:16 ` [PULL 26/45] target/riscv: Set pc_succ_insn for !rvc illegal insn Alistair Francis
2022-12-19 2:16 ` [PULL 27/45] target/riscv: Simplify helper_sret() a little bit Alistair Francis
2022-12-19 2:16 ` [PULL 28/45] target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+ Alistair Francis
2022-12-19 2:16 ` [PULL 29/45] RISC-V: Add Zawrs ISA extension support Alistair Francis
2022-12-19 2:16 ` [PULL 30/45] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Alistair Francis
2022-12-19 2:16 ` [PULL 31/45] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers Alistair Francis
2022-12-19 2:16 ` [PULL 32/45] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC Alistair Francis
2022-12-19 2:16 ` [PULL 33/45] hw/riscv: Sort machines Kconfig options in alphabetical order Alistair Francis
2022-12-19 2:16 ` [PULL 34/45] hw/riscv: spike: Remove misleading comments Alistair Francis
2022-12-19 2:16 ` [PULL 35/45] hw/intc: sifive_plic: Drop PLICMode_H Alistair Francis
2022-12-19 2:16 ` [PULL 36/45] hw/intc: sifive_plic: Improve robustness of the PLIC config parser Alistair Francis
2022-12-19 2:16 ` [PULL 37/45] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize() Alistair Francis
2022-12-19 2:16 ` [PULL 38/45] hw/intc: sifive_plic: Update "num-sources" property default value Alistair Francis
2022-12-19 2:16 ` [PULL 39/45] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC Alistair Francis
2022-12-19 2:16 ` [PULL 40/45] hw/riscv: sifive_e: " Alistair Francis
2022-12-19 2:16 ` [PULL 41/45] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev" Alistair Francis
2022-12-19 2:17 ` [PULL 42/45] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb Alistair Francis
2022-12-19 2:17 ` [PULL 43/45] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0 Alistair Francis
2022-12-19 2:17 ` [PULL 44/45] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization Alistair Francis
2022-12-19 2:17 ` [PULL 45/45] hw/intc: sifive_plic: Fix the pending register range check Alistair Francis
2022-12-19 15:11 ` [PULL 00/45] riscv-to-apply queue Peter Maydell
2022-12-19 23:28 ` Alistair Francis
2022-12-20 15:32 ` Peter Maydell
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