From: Bernhard Beschow <shentey@gmail.com>
To: qemu-devel@nongnu.org
Cc: "Richard Henderson" <richard.henderson@linaro.org>,
"Igor Mammedov" <imammedo@redhat.com>,
"Aurelien Jarno" <aurelien@aurel32.net>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
qemu-block@nongnu.org, "Hervé Poussineau" <hpoussin@reactos.org>,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"Ani Sinha" <ani@anisinha.ca>, "John Snow" <jsnow@redhat.com>,
"Gerd Hoffmann" <kraxel@redhat.com>,
"Michael S. Tsirkin" <mst@redhat.com>,
"Eduardo Habkost" <eduardo@habkost.net>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
"Bernhard Beschow" <shentey@gmail.com>
Subject: [PATCH v4 16/30] hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS
Date: Wed, 21 Dec 2022 17:59:49 +0100 [thread overview]
Message-ID: <20221221170003.2929-17-shentey@gmail.com> (raw)
In-Reply-To: <20221221170003.2929-1-shentey@gmail.com>
PIIX_NUM_PIC_IRQS is assumed to be the same as ISA_NUM_IRQS, otherwise
inconsistencies can occur.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20221022150508.26830-21-shentey@gmail.com>
---
hw/isa/piix3.c | 8 ++++----
include/hw/southbridge/piix.h | 5 ++---
2 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index c33a3faa2f..a1fd1e0d3e 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -52,7 +52,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
uint64_t mask;
pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
- if (pic_irq >= PIIX_NUM_PIC_IRQS) {
+ if (pic_irq >= ISA_NUM_IRQS) {
return;
}
@@ -66,7 +66,7 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
int pic_irq;
pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
- if (pic_irq >= PIIX_NUM_PIC_IRQS) {
+ if (pic_irq >= ISA_NUM_IRQS) {
return;
}
@@ -87,7 +87,7 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
int irq = piix3->dev.config[PIIX_PIRQCA + pin];
PCIINTxRoute route;
- if (irq < PIIX_NUM_PIC_IRQS) {
+ if (irq < ISA_NUM_IRQS) {
route.mode = PCI_INTX_ENABLED;
route.irq = irq;
} else {
@@ -119,7 +119,7 @@ static void piix3_write_config(PCIDevice *dev,
pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
piix3_update_irq_levels(piix3);
- for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
+ for (pic_irq = 0; pic_irq < ISA_NUM_IRQS; pic_irq++) {
piix3_set_irq_pic(piix3, pic_irq);
}
}
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index c4e6e9f827..39c31da9ad 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -32,7 +32,6 @@
*/
#define PIIX_RCR_IOPORT 0xcf9
-#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
struct PIIXState {
@@ -44,10 +43,10 @@ struct PIIXState {
* So one PIC level is tracked by PIIX_NUM_PIRQS bits.
*
* PIRQ is mapped to PIC pins, we track it by
- * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
+ * PIIX_NUM_PIRQS * ISA_NUM_IRQS = 64 bits with
* pic_irq * PIIX_NUM_PIRQS + pirq
*/
-#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
+#if ISA_NUM_IRQS * PIIX_NUM_PIRQS > 64
#error "unable to encode pic state in 64bit in pic_levels."
#endif
uint64_t pic_levels;
--
2.39.0
next prev parent reply other threads:[~2022-12-21 17:14 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-21 16:59 [PATCH v4 00/30] This series consolidates the implementations of the PIIX3 and PIIX4 south Bernhard Beschow
2022-12-21 16:59 ` [PATCH v4 01/30] hw/mips/malta: Introduce PIIX4_PCI_DEVFN definition Bernhard Beschow
2022-12-21 16:59 ` [PATCH v4 02/30] hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader Bernhard Beschow
2022-12-21 16:59 ` [PATCH v4 03/30] hw/isa/piix4: Correct IRQRC[A:D] reset values Bernhard Beschow
2022-12-21 16:59 ` [PATCH v4 04/30] hw/mips/Kconfig: Track Malta's PIIX dependencies via Kconfig Bernhard Beschow
2022-12-21 16:59 ` [PATCH v4 05/30] hw/usb/hcd-uhci: Introduce TYPE_ defines for device models Bernhard Beschow
2022-12-21 16:59 ` [PATCH v4 06/30] hw/i386/pc_piix: Associate pci_map_irq_fn as soon as PCI bus is created Bernhard Beschow
2023-01-04 19:42 ` Bernhard Beschow
2022-12-21 16:59 ` [PATCH v4 07/30] hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 south bridge Bernhard Beschow
2022-12-21 16:59 ` [PATCH v4 08/30] hw/i386/pc: Create RTC controllers in south bridges Bernhard Beschow
2023-01-02 17:03 ` Thomas Huth
2023-01-02 18:25 ` Bernhard Beschow
2023-01-03 8:51 ` Thomas Huth
2022-12-21 16:59 ` [PATCH v4 09/30] hw/i386/pc: No need for rtc_state to be an out-parameter Bernhard Beschow
2023-01-03 8:52 ` Thomas Huth
2022-12-21 16:59 ` [PATCH v4 10/30] hw/isa/piix3: Create USB controller in host device Bernhard Beschow
2022-12-21 16:59 ` [PATCH v4 11/30] hw/isa/piix3: Create power management " Bernhard Beschow
2022-12-21 16:59 ` [PATCH v4 12/30] hw/core: Introduce proxy-pic Bernhard Beschow
2023-01-04 14:37 ` Philippe Mathieu-Daudé
2023-01-04 16:01 ` Bernhard Beschow
2023-01-04 16:35 ` Philippe Mathieu-Daudé
2023-01-04 16:51 ` Mark Cave-Ayland
2023-01-04 20:12 ` Bernhard Beschow
2023-01-04 20:31 ` Philippe Mathieu-Daudé
2023-01-04 20:57 ` Bernhard Beschow
2023-01-04 19:53 ` [PATCH] " Bernhard Beschow
2023-01-04 22:22 ` Mark Cave-Ayland
2023-01-05 9:50 ` Bernhard Beschow
2023-01-05 14:45 ` Bernhard Beschow
2022-12-21 16:59 ` [PATCH v4 13/30] hw/isa/piix3: Create Proxy PIC in host device Bernhard Beschow
2022-12-21 16:59 ` [PATCH v4 14/30] hw/isa/piix3: Create IDE controller " Bernhard Beschow
2022-12-21 16:59 ` [PATCH v4 15/30] hw/isa/piix3: Wire up ACPI interrupt internally Bernhard Beschow
2022-12-21 16:59 ` Bernhard Beschow [this message]
2022-12-21 16:59 ` [PATCH v4 17/30] hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4 Bernhard Beschow
2022-12-21 16:59 ` [PATCH v4 18/30] hw/isa/piix3: Rename piix3_reset() " Bernhard Beschow
2022-12-21 16:59 ` [PATCH v4 19/30] hw/isa/piix3: Drop the "3" from PIIX base class Bernhard Beschow
2022-12-21 16:59 ` [PATCH v4 20/30] hw/isa/piix4: Make PIIX4's ACPI and USB functions optional Bernhard Beschow
2022-12-21 16:59 ` [PATCH v4 21/30] hw/isa/piix4: Remove unused inbound ISA interrupt lines Bernhard Beschow
2022-12-21 16:59 ` [PATCH v4 22/30] hw/isa/piix4: Use Proxy PIC device Bernhard Beschow
2022-12-21 16:59 ` [PATCH v4 23/30] hw/isa/piix4: Reuse struct PIIXState from PIIX3 Bernhard Beschow
2022-12-21 16:59 ` [PATCH v4 24/30] hw/isa/piix4: Rename reset control operations to match PIIX3 Bernhard Beschow
2022-12-21 16:59 ` [PATCH v4 25/30] hw/isa/piix3: Merge hw/isa/piix4.c Bernhard Beschow
2022-12-21 16:59 ` [PATCH v4 26/30] hw/isa/piix: Harmonize names of reset control memory regions Bernhard Beschow
2022-12-21 17:00 ` [PATCH v4 27/30] hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 Bernhard Beschow
2022-12-21 17:00 ` [PATCH v4 28/30] hw/isa/piix: Rename functions to be shared for interrupt triggering Bernhard Beschow
2022-12-21 17:00 ` [PATCH v4 29/30] hw/isa/piix: Consolidate IRQ triggering Bernhard Beschow
2022-12-21 17:00 ` [PATCH v4 30/30] hw/isa/piix: Share PIIX3's base class with PIIX4 Bernhard Beschow
2022-12-21 19:15 ` [PATCH v4 00/30] This series consolidates the implementations of the PIIX3 and PIIX4 south Philippe Mathieu-Daudé
2022-12-21 23:13 ` Bernhard Beschow
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