From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com,
Mayuresh Chitale <mchitale@ventanamicro.com>,
Weiwei Li <liweiwei@iscas.ac.cn>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL v2 11/45] target/riscv: generate virtual instruction exception
Date: Thu, 22 Dec 2022 08:39:48 +1000 [thread overview]
Message-ID: <20221221224022.425831-12-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20221221224022.425831-1-alistair.francis@opensource.wdc.com>
From: Mayuresh Chitale <mchitale@ventanamicro.com>
This patch adds a mechanism to generate a virtual instruction
instruction exception instead of an illegal instruction exception
during instruction decode when virt is enabled.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221016124726.102129-4-mchitale@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/translate.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index db123da5ec..8b0bd38bb2 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -76,6 +76,7 @@ typedef struct DisasContext {
to reset this known value. */
int frm;
RISCVMXL ol;
+ bool virt_inst_excp;
bool virt_enabled;
const RISCVCPUConfig *cfg_ptr;
bool hlsx;
@@ -243,7 +244,11 @@ static void gen_exception_illegal(DisasContext *ctx)
{
tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
offsetof(CPURISCVState, bins));
- generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
+ if (ctx->virt_inst_excp) {
+ generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT);
+ } else {
+ generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
+ }
}
static void gen_exception_inst_addr_mis(DisasContext *ctx)
@@ -1062,6 +1067,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
{ has_XVentanaCondOps_p, decode_XVentanaCodeOps },
};
+ ctx->virt_inst_excp = false;
/* Check for compressed insn */
if (insn_len(opcode) == 2) {
if (!has_ext(ctx, RVC)) {
--
2.38.1
next prev parent reply other threads:[~2022-12-21 22:41 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-21 22:39 [PULL v2 00/45] riscv-to-apply queue Alistair Francis
2022-12-21 22:39 ` [PULL v2 01/45] target/riscv: Fix PMP propagation for tlb Alistair Francis
2022-12-21 22:39 ` [PULL v2 02/45] hw/registerfields: add `FIELDx_1CLEAR()` macro Alistair Francis
2022-12-21 22:39 ` [PULL v2 03/45] hw/ssi/ibex_spi: implement `FIELD32_1CLEAR` macro Alistair Francis
2023-01-04 9:38 ` Philippe Mathieu-Daudé
2023-01-04 12:30 ` Alistair Francis
2023-01-04 22:55 ` Wilfred Mallawa
2022-12-21 22:39 ` [PULL v2 04/45] tcg/riscv: Fix range matched by TCG_CT_CONST_M12 Alistair Francis
2022-12-21 22:39 ` [PULL v2 05/45] tcg/riscv: Fix reg overlap case in tcg_out_addsub2 Alistair Francis
2022-12-21 22:39 ` [PULL v2 06/45] tcg/riscv: Fix base register for user-only qemu_ld/st Alistair Francis
2022-12-21 22:39 ` [PULL v2 07/45] hw/riscv/opentitan: bump opentitan Alistair Francis
2022-12-21 22:39 ` [PULL v2 08/45] hw/riscv/opentitan: add aon_timer base unimpl Alistair Francis
2022-12-21 22:39 ` [PULL v2 09/45] target/riscv: Add smstateen support Alistair Francis
2022-12-21 22:39 ` [PULL v2 10/45] target/riscv: smstateen check for h/s/envcfg Alistair Francis
2022-12-21 22:39 ` Alistair Francis [this message]
2022-12-21 22:39 ` [PULL v2 12/45] target/riscv: Add itrigger support when icount is not enabled Alistair Francis
2022-12-21 22:39 ` [PULL v2 13/45] target/riscv: Add itrigger support when icount is enabled Alistair Francis
2022-12-21 22:39 ` [PULL v2 14/45] target/riscv: Enable native debug itrigger Alistair Francis
2022-12-21 22:39 ` [PULL v2 15/45] target/riscv: Add itrigger_enabled field to CPURISCVState Alistair Francis
2022-12-21 22:39 ` [PULL v2 16/45] hw/intc: sifive_plic: Renumber the S irqs for numa support Alistair Francis
2022-12-21 22:39 ` [PULL v2 17/45] target/riscv: Typo fix in sstc() predicate Alistair Francis
2022-12-21 22:39 ` [PULL v2 18/45] hw/riscv: virt: Remove the redundant ipi-id property Alistair Francis
2022-12-21 22:39 ` [PULL v2 19/45] target/riscv: support cache-related PMU events in virtual mode Alistair Francis
2022-12-21 22:39 ` [PULL v2 20/45] target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state() Alistair Francis
2022-12-21 22:39 ` [PULL v2 21/45] hw/misc: pfsoc: add fabric clocks to ioscb Alistair Francis
2022-12-21 22:39 ` [PULL v2 22/45] hw/riscv: pfsoc: add missing FICs as unimplemented Alistair Francis
2022-12-21 22:40 ` [PULL v2 23/45] hw/{misc, riscv}: pfsoc: add system controller " Alistair Francis
2022-12-21 22:40 ` [PULL v2 24/45] hw/intc: sifive_plic: fix out-of-bound access of source_priority array Alistair Francis
2022-12-21 22:40 ` [PULL v2 25/45] target/riscv: Fix mret exception cause when no pmp rule is configured Alistair Francis
2022-12-21 22:40 ` [PULL v2 26/45] target/riscv: Set pc_succ_insn for !rvc illegal insn Alistair Francis
2022-12-21 22:40 ` [PULL v2 27/45] target/riscv: Simplify helper_sret() a little bit Alistair Francis
2022-12-21 22:40 ` [PULL v2 28/45] target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+ Alistair Francis
2022-12-21 22:40 ` [PULL v2 29/45] RISC-V: Add Zawrs ISA extension support Alistair Francis
2022-12-21 22:40 ` [PULL v2 30/45] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Alistair Francis
2022-12-21 22:40 ` [PULL v2 31/45] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers Alistair Francis
2022-12-21 22:40 ` [PULL v2 32/45] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC Alistair Francis
2022-12-21 22:40 ` [PULL v2 33/45] hw/riscv: Sort machines Kconfig options in alphabetical order Alistair Francis
2022-12-21 22:40 ` [PULL v2 34/45] hw/riscv: spike: Remove misleading comments Alistair Francis
2022-12-21 22:40 ` [PULL v2 35/45] hw/intc: sifive_plic: Drop PLICMode_H Alistair Francis
2022-12-21 22:40 ` [PULL v2 36/45] hw/intc: sifive_plic: Improve robustness of the PLIC config parser Alistair Francis
2022-12-21 22:40 ` [PULL v2 37/45] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize() Alistair Francis
2022-12-21 22:40 ` [PULL v2 38/45] hw/intc: sifive_plic: Update "num-sources" property default value Alistair Francis
2022-12-21 22:40 ` [PULL v2 39/45] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC Alistair Francis
2022-12-21 22:40 ` [PULL v2 40/45] hw/riscv: sifive_e: " Alistair Francis
2022-12-21 22:40 ` [PULL v2 41/45] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev" Alistair Francis
2022-12-21 22:40 ` [PULL v2 42/45] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb Alistair Francis
2022-12-21 22:40 ` [PULL v2 43/45] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0 Alistair Francis
2022-12-21 22:40 ` [PULL v2 44/45] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization Alistair Francis
2022-12-21 22:40 ` [PULL v2 45/45] hw/intc: sifive_plic: Fix the pending register range check Alistair Francis
2023-01-04 9:20 ` [PULL v2 00/45] riscv-to-apply queue Thomas Huth
2023-01-04 14:53 ` Peter Maydell
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