From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com,
"Richard Henderson" <richard.henderson@linaro.org>,
qemu-stable@nongnu.org,
"Alistair Francis" <alistair.francis@wdc.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PULL v2 26/45] target/riscv: Set pc_succ_insn for !rvc illegal insn
Date: Thu, 22 Dec 2022 08:40:03 +1000 [thread overview]
Message-ID: <20221221224022.425831-27-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20221221224022.425831-1-alistair.francis@opensource.wdc.com>
From: Richard Henderson <richard.henderson@linaro.org>
Failure to set pc_succ_insn may result in a TB covering zero bytes,
which triggers an assert within the code generator.
Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1224
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221203175744.151365-1-richard.henderson@linaro.org>
[ Changes by AF:
- Add missing run-plugin-test-noc-% line
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/translate.c | 12 ++++--------
tests/tcg/Makefile.target | 2 ++
tests/tcg/riscv64/Makefile.target | 6 ++++++
tests/tcg/riscv64/test-noc.S | 32 +++++++++++++++++++++++++++++++
4 files changed, 44 insertions(+), 8 deletions(-)
create mode 100644 tests/tcg/riscv64/test-noc.S
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index cd5eb25ee8..160aefc3df 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1096,14 +1096,10 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
ctx->virt_inst_excp = false;
/* Check for compressed insn */
if (insn_len(opcode) == 2) {
- if (!has_ext(ctx, RVC)) {
- gen_exception_illegal(ctx);
- } else {
- ctx->opcode = opcode;
- ctx->pc_succ_insn = ctx->base.pc_next + 2;
- if (decode_insn16(ctx, opcode)) {
- return;
- }
+ ctx->opcode = opcode;
+ ctx->pc_succ_insn = ctx->base.pc_next + 2;
+ if (has_ext(ctx, RVC) && decode_insn16(ctx, opcode)) {
+ return;
}
} else {
uint32_t opcode32 = opcode;
diff --git a/tests/tcg/Makefile.target b/tests/tcg/Makefile.target
index 75257f2b29..14bc013181 100644
--- a/tests/tcg/Makefile.target
+++ b/tests/tcg/Makefile.target
@@ -117,6 +117,8 @@ endif
%: %.c
$(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS)
+%: %.S
+ $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS)
else
# For softmmu targets we include a different Makefile fragement as the
# build options for bare programs are usually pretty different. They
diff --git a/tests/tcg/riscv64/Makefile.target b/tests/tcg/riscv64/Makefile.target
index b5b89dfb0e..cc3ed65ffd 100644
--- a/tests/tcg/riscv64/Makefile.target
+++ b/tests/tcg/riscv64/Makefile.target
@@ -4,3 +4,9 @@
VPATH += $(SRC_PATH)/tests/tcg/riscv64
TESTS += test-div
TESTS += noexec
+
+# Disable compressed instructions for test-noc
+TESTS += test-noc
+test-noc: LDFLAGS = -nostdlib -static
+run-test-noc: QEMU_OPTS += -cpu rv64,c=false
+run-plugin-test-noc-%: QEMU_OPTS += -cpu rv64,c=false
diff --git a/tests/tcg/riscv64/test-noc.S b/tests/tcg/riscv64/test-noc.S
new file mode 100644
index 0000000000..e29d60c8b3
--- /dev/null
+++ b/tests/tcg/riscv64/test-noc.S
@@ -0,0 +1,32 @@
+#include <asm/unistd.h>
+
+ .text
+ .globl _start
+_start:
+ .option norvc
+ li a0, 4 /* SIGILL */
+ la a1, sa
+ li a2, 0
+ li a3, 8
+ li a7, __NR_rt_sigaction
+ scall
+
+ .option rvc
+ li a0, 1
+ j exit
+ .option norvc
+
+pass:
+ li a0, 0
+exit:
+ li a7, __NR_exit
+ scall
+
+ .data
+ /* struct kernel_sigaction sa = { .sa_handler = pass }; */
+ .type sa, @object
+ .size sa, 32
+sa:
+ .dword pass
+ .zero 24
+
--
2.38.1
next prev parent reply other threads:[~2022-12-21 22:57 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-21 22:39 [PULL v2 00/45] riscv-to-apply queue Alistair Francis
2022-12-21 22:39 ` [PULL v2 01/45] target/riscv: Fix PMP propagation for tlb Alistair Francis
2022-12-21 22:39 ` [PULL v2 02/45] hw/registerfields: add `FIELDx_1CLEAR()` macro Alistair Francis
2022-12-21 22:39 ` [PULL v2 03/45] hw/ssi/ibex_spi: implement `FIELD32_1CLEAR` macro Alistair Francis
2023-01-04 9:38 ` Philippe Mathieu-Daudé
2023-01-04 12:30 ` Alistair Francis
2023-01-04 22:55 ` Wilfred Mallawa
2022-12-21 22:39 ` [PULL v2 04/45] tcg/riscv: Fix range matched by TCG_CT_CONST_M12 Alistair Francis
2022-12-21 22:39 ` [PULL v2 05/45] tcg/riscv: Fix reg overlap case in tcg_out_addsub2 Alistair Francis
2022-12-21 22:39 ` [PULL v2 06/45] tcg/riscv: Fix base register for user-only qemu_ld/st Alistair Francis
2022-12-21 22:39 ` [PULL v2 07/45] hw/riscv/opentitan: bump opentitan Alistair Francis
2022-12-21 22:39 ` [PULL v2 08/45] hw/riscv/opentitan: add aon_timer base unimpl Alistair Francis
2022-12-21 22:39 ` [PULL v2 09/45] target/riscv: Add smstateen support Alistair Francis
2022-12-21 22:39 ` [PULL v2 10/45] target/riscv: smstateen check for h/s/envcfg Alistair Francis
2022-12-21 22:39 ` [PULL v2 11/45] target/riscv: generate virtual instruction exception Alistair Francis
2022-12-21 22:39 ` [PULL v2 12/45] target/riscv: Add itrigger support when icount is not enabled Alistair Francis
2022-12-21 22:39 ` [PULL v2 13/45] target/riscv: Add itrigger support when icount is enabled Alistair Francis
2022-12-21 22:39 ` [PULL v2 14/45] target/riscv: Enable native debug itrigger Alistair Francis
2022-12-21 22:39 ` [PULL v2 15/45] target/riscv: Add itrigger_enabled field to CPURISCVState Alistair Francis
2022-12-21 22:39 ` [PULL v2 16/45] hw/intc: sifive_plic: Renumber the S irqs for numa support Alistair Francis
2022-12-21 22:39 ` [PULL v2 17/45] target/riscv: Typo fix in sstc() predicate Alistair Francis
2022-12-21 22:39 ` [PULL v2 18/45] hw/riscv: virt: Remove the redundant ipi-id property Alistair Francis
2022-12-21 22:39 ` [PULL v2 19/45] target/riscv: support cache-related PMU events in virtual mode Alistair Francis
2022-12-21 22:39 ` [PULL v2 20/45] target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state() Alistair Francis
2022-12-21 22:39 ` [PULL v2 21/45] hw/misc: pfsoc: add fabric clocks to ioscb Alistair Francis
2022-12-21 22:39 ` [PULL v2 22/45] hw/riscv: pfsoc: add missing FICs as unimplemented Alistair Francis
2022-12-21 22:40 ` [PULL v2 23/45] hw/{misc, riscv}: pfsoc: add system controller " Alistair Francis
2022-12-21 22:40 ` [PULL v2 24/45] hw/intc: sifive_plic: fix out-of-bound access of source_priority array Alistair Francis
2022-12-21 22:40 ` [PULL v2 25/45] target/riscv: Fix mret exception cause when no pmp rule is configured Alistair Francis
2022-12-21 22:40 ` Alistair Francis [this message]
2022-12-21 22:40 ` [PULL v2 27/45] target/riscv: Simplify helper_sret() a little bit Alistair Francis
2022-12-21 22:40 ` [PULL v2 28/45] target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+ Alistair Francis
2022-12-21 22:40 ` [PULL v2 29/45] RISC-V: Add Zawrs ISA extension support Alistair Francis
2022-12-21 22:40 ` [PULL v2 30/45] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Alistair Francis
2022-12-21 22:40 ` [PULL v2 31/45] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers Alistair Francis
2022-12-21 22:40 ` [PULL v2 32/45] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC Alistair Francis
2022-12-21 22:40 ` [PULL v2 33/45] hw/riscv: Sort machines Kconfig options in alphabetical order Alistair Francis
2022-12-21 22:40 ` [PULL v2 34/45] hw/riscv: spike: Remove misleading comments Alistair Francis
2022-12-21 22:40 ` [PULL v2 35/45] hw/intc: sifive_plic: Drop PLICMode_H Alistair Francis
2022-12-21 22:40 ` [PULL v2 36/45] hw/intc: sifive_plic: Improve robustness of the PLIC config parser Alistair Francis
2022-12-21 22:40 ` [PULL v2 37/45] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize() Alistair Francis
2022-12-21 22:40 ` [PULL v2 38/45] hw/intc: sifive_plic: Update "num-sources" property default value Alistair Francis
2022-12-21 22:40 ` [PULL v2 39/45] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC Alistair Francis
2022-12-21 22:40 ` [PULL v2 40/45] hw/riscv: sifive_e: " Alistair Francis
2022-12-21 22:40 ` [PULL v2 41/45] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev" Alistair Francis
2022-12-21 22:40 ` [PULL v2 42/45] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb Alistair Francis
2022-12-21 22:40 ` [PULL v2 43/45] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0 Alistair Francis
2022-12-21 22:40 ` [PULL v2 44/45] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization Alistair Francis
2022-12-21 22:40 ` [PULL v2 45/45] hw/intc: sifive_plic: Fix the pending register range check Alistair Francis
2023-01-04 9:20 ` [PULL v2 00/45] riscv-to-apply queue Thomas Huth
2023-01-04 14:53 ` Peter Maydell
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