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envelope-from=prvs=3472792e2=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Wilfred Mallawa use the `FIELD32_1CLEAR` macro to implement register `rw1c` functionality to `ibex_spi`. This change was tested by running the `SPI_HOST` from TockOS. Signed-off-by: Wilfred Mallawa Reviewed-by: Alistair Francis Message-Id: <20221017054950.317584-3-wilfred.mallawa@opensource.wdc.com> Signed-off-by: Alistair Francis --- hw/ssi/ibex_spi_host.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c index 57df462e3c..0a456cd1ed 100644 --- a/hw/ssi/ibex_spi_host.c +++ b/hw/ssi/ibex_spi_host.c @@ -342,7 +342,7 @@ static void ibex_spi_host_write(void *opaque, hwaddr = addr, { IbexSPIHostState *s =3D opaque; uint32_t val32 =3D val64; - uint32_t shift_mask =3D 0xff, status =3D 0, data =3D 0; + uint32_t shift_mask =3D 0xff, status =3D 0; uint8_t txqd_len; =20 trace_ibex_spi_host_write(addr, size, val64); @@ -355,12 +355,11 @@ static void ibex_spi_host_write(void *opaque, hwadd= r addr, case IBEX_SPI_HOST_INTR_STATE: /* rw1c status register */ if (FIELD_EX32(val32, INTR_STATE, ERROR)) { - data =3D FIELD_DP32(data, INTR_STATE, ERROR, 0); + s->regs[addr] =3D FIELD32_1CLEAR(s->regs[addr], INTR_STATE, = ERROR); } if (FIELD_EX32(val32, INTR_STATE, SPI_EVENT)) { - data =3D FIELD_DP32(data, INTR_STATE, SPI_EVENT, 0); + s->regs[addr] =3D FIELD32_1CLEAR(s->regs[addr], INTR_STATE, = SPI_EVENT); } - s->regs[addr] =3D data; break; case IBEX_SPI_HOST_INTR_ENABLE: s->regs[addr] =3D val32; @@ -505,27 +504,25 @@ static void ibex_spi_host_write(void *opaque, hwadd= r addr, * When an error occurs, the corresponding bit must be cleared * here before issuing any further commands */ - status =3D s->regs[addr]; /* rw1c status register */ if (FIELD_EX32(val32, ERROR_STATUS, CMDBUSY)) { - status =3D FIELD_DP32(status, ERROR_STATUS, CMDBUSY, 0); + s->regs[addr] =3D FIELD32_1CLEAR(s->regs[addr], ERROR_STATUS= , CMDBUSY); } if (FIELD_EX32(val32, ERROR_STATUS, OVERFLOW)) { - status =3D FIELD_DP32(status, ERROR_STATUS, OVERFLOW, 0); + s->regs[addr] =3D FIELD32_1CLEAR(s->regs[addr], ERROR_STATUS= , OVERFLOW); } if (FIELD_EX32(val32, ERROR_STATUS, UNDERFLOW)) { - status =3D FIELD_DP32(status, ERROR_STATUS, UNDERFLOW, 0); + s->regs[addr] =3D FIELD32_1CLEAR(s->regs[addr], ERROR_STATUS= , UNDERFLOW); } if (FIELD_EX32(val32, ERROR_STATUS, CMDINVAL)) { - status =3D FIELD_DP32(status, ERROR_STATUS, CMDINVAL, 0); + s->regs[addr] =3D FIELD32_1CLEAR(s->regs[addr], ERROR_STATUS= , CMDINVAL); } if (FIELD_EX32(val32, ERROR_STATUS, CSIDINVAL)) { - status =3D FIELD_DP32(status, ERROR_STATUS, CSIDINVAL, 0); + s->regs[addr] =3D FIELD32_1CLEAR(s->regs[addr], ERROR_STATUS= , CSIDINVAL); } if (FIELD_EX32(val32, ERROR_STATUS, ACCESSINVAL)) { - status =3D FIELD_DP32(status, ERROR_STATUS, ACCESSINVAL, 0); + s->regs[addr] =3D FIELD32_1CLEAR(s->regs[addr], ERROR_STATUS= , ACCESSINVAL); } - s->regs[addr] =3D status; break; case IBEX_SPI_HOST_EVENT_ENABLE: /* Controls which classes of SPI events raise an interrupt. */ --=20 2.38.1