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([2607:fb90:8060:51a2:184b:6e49:c396:be2]) by smtp.gmail.com with ESMTPSA id v2-20020a05620a440200b006fed2788751sm23042354qkp.76.2023.01.03.10.17.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jan 2023 10:17:39 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, berrange@redhat.com, eduardo@habkost.net, armbru@redhat.com, ajones@ventanamicro.com, alex.bennee@linaro.org Subject: [RFC PATCH 17/40] target/arm: Copy cp_regs from ARMCPUClass Date: Tue, 3 Jan 2023 10:16:23 -0800 Message-Id: <20230103181646.55711-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230103181646.55711-1-richard.henderson@linaro.org> References: <20230103181646.55711-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::a2d; envelope-from=richard.henderson@linaro.org; helo=mail-vk1-xa2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Create a hash table of cpregs in ARMCPUClass and copy to the instance in arm_cpu_init. Population of this new table will come in a future patch. Signed-off-by: Richard Henderson --- target/arm/cpu-qom.h | 3 +++ target/arm/cpu.c | 23 +++++++++++++++++++++-- 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index 832b2cccf9..36d7fa9779 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -111,6 +111,9 @@ struct ARMCPUClass { DeviceRealize parent_realize; ResettablePhases parent_phases; + /* Coprocessor information */ + GHashTable *cp_regs; + /* 'compatible' string for this CPU for Linux device trees */ const char *dtb_compatible; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a46fa424d3..da58f1fae7 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1178,14 +1178,29 @@ uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz) return (Aff1 << ARM_AFF1_SHIFT) | Aff0; } +static void copy_cp_regs_1(gpointer key, gpointer value, gpointer user) +{ + GHashTable *new_table = user; + ARMCPRegInfo *new_reg = g_memdup(value, sizeof(ARMCPRegInfo)); + bool ok = g_hash_table_insert(new_table, key, new_reg); + g_assert(ok); +} + +static GHashTable *copy_cp_regs(GHashTable *cp_regs) +{ + GHashTable *ret = g_hash_table_new_full(g_direct_hash, g_direct_equal, + NULL, g_free); + + g_hash_table_foreach(cp_regs, copy_cp_regs_1, ret); + return ret; +} + static void arm_cpu_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); cpu_set_cpustate_pointers(cpu); - cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal, - NULL, g_free); QLIST_INIT(&cpu->pre_el_change_hooks); QLIST_INIT(&cpu->el_change_hooks); @@ -1219,6 +1234,8 @@ static void arm_cpu_initfn(Object *obj) cpu->gic_pribits = acc->gic_pribits; cpu->kvm_target = acc->kvm_target; + cpu->cp_regs = copy_cp_regs(acc->cp_regs); + #ifdef CONFIG_USER_ONLY # ifdef TARGET_AARCH64 /* @@ -2337,6 +2354,8 @@ static void arm_cpu_leaf_class_init(ObjectClass *oc, void *data) const ARMCPUInfo *info = data; acc->info = info; + acc->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal, + NULL, g_free); if (info->class_init) { info->class_init(acc); } -- 2.34.1