From: Fabiano Rosas <farosas@suse.de>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, "Peter Maydell" <peter.maydell@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Claudio Fontana" <cfontana@suse.de>,
"Eduardo Habkost" <ehabkost@redhat.com>,
"Alexander Graf" <agraf@csgraf.de>,
"Cornelia Huck" <cohuck@redhat.com>
Subject: [RFC PATCH 02/27] target/arm: Fix checkpatch space errors in helper.c
Date: Wed, 4 Jan 2023 18:58:10 -0300 [thread overview]
Message-ID: <20230104215835.24692-3-farosas@suse.de> (raw)
In-Reply-To: <20230104215835.24692-1-farosas@suse.de>
Fix the following:
ERROR: spaces required around that '|' (ctx:VxV)
ERROR: space required before the open parenthesis '('
ERROR: spaces required around that '+' (ctx:VxB)
ERROR: space prohibited between function name and open parenthesis '('
(the last two still have some occurrences in macros which I left
behind because it might impact readability)
Reviewed-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
---
target/arm/helper.c | 42 +++++++++++++++++++++---------------------
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 6703936a28..18e4680912 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -205,7 +205,7 @@ static void add_cpreg_to_list(gpointer key, gpointer opaque)
uint32_t regidx = (uintptr_t)key;
const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
- if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
+ if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) {
cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
/* The value array need not be initialized at this point */
cpu->cpreg_array_len++;
@@ -219,7 +219,7 @@ static void count_cpreg(gpointer key, gpointer opaque)
ri = g_hash_table_lookup(cpu->cp_regs, key);
- if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
+ if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) {
cpu->cpreg_array_len++;
}
}
@@ -2350,11 +2350,11 @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
.resetfn = arm_cp_reset_ignore },
{ .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
- .access = PL0_R|PL1_W,
+ .access = PL0_R | PL1_W,
.fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]),
.resetvalue = 0},
{ .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
- .access = PL0_R|PL1_W,
+ .access = PL0_R | PL1_W,
.bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
.resetfn = arm_cp_reset_ignore },
@@ -4099,17 +4099,17 @@ static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
.resetvalue = 0 },
/* The cache ops themselves: these all NOP for QEMU */
{ .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
- .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+ .access = PL1_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
{ .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
- .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+ .access = PL1_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
{ .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
- .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+ .access = PL0_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
{ .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
- .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+ .access = PL0_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
{ .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
- .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+ .access = PL0_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
{ .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
- .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+ .access = PL1_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
};
static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
@@ -8392,7 +8392,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
ARMCPRegInfo cbar = {
.name = "CBAR",
.cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
- .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
+ .access = PL1_R | PL3_W, .resetvalue = cpu->reset_cbar,
.fieldoffset = offsetof(CPUARMState,
cp15.c15_config_base_address)
};
@@ -9359,11 +9359,11 @@ static void switch_mode(CPUARMState *env, int mode)
return;
if (old_mode == ARM_CPU_MODE_FIQ) {
- memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
- memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
+ memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
+ memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
} else if (mode == ARM_CPU_MODE_FIQ) {
- memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
- memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
+ memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
+ memcpy(env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
}
i = bank_number(old_mode);
@@ -10867,7 +10867,7 @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
RESULT(sum, n, 16); \
if (sum >= 0) \
ge |= 3 << (n * 2); \
- } while(0)
+ } while (0)
#define SARITH8(a, b, n, op) do { \
int32_t sum; \
@@ -10875,7 +10875,7 @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
RESULT(sum, n, 8); \
if (sum >= 0) \
ge |= 1 << n; \
- } while(0)
+ } while (0)
#define ADD16(a, b, n) SARITH16(a, b, n, +)
@@ -10894,7 +10894,7 @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
RESULT(sum, n, 16); \
if ((sum >> 16) == 1) \
ge |= 3 << (n * 2); \
- } while(0)
+ } while (0)
#define ADD8(a, b, n) do { \
uint32_t sum; \
@@ -10902,7 +10902,7 @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
RESULT(sum, n, 8); \
if ((sum >> 8) == 1) \
ge |= 1 << n; \
- } while(0)
+ } while (0)
#define SUB16(a, b, n) do { \
uint32_t sum; \
@@ -10910,7 +10910,7 @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
RESULT(sum, n, 16); \
if ((sum >> 16) == 0) \
ge |= 3 << (n * 2); \
- } while(0)
+ } while (0)
#define SUB8(a, b, n) do { \
uint32_t sum; \
@@ -10918,7 +10918,7 @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
RESULT(sum, n, 8); \
if ((sum >> 8) == 0) \
ge |= 1 << n; \
- } while(0)
+ } while (0)
#define PFX u
#define ARITH_GE
--
2.35.3
next prev parent reply other threads:[~2023-01-04 22:04 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-04 21:58 [RFC PATCH 00/27] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
2023-01-04 21:58 ` [RFC PATCH 01/27] target/arm: Fix checkpatch comment style warnings in helper.c Fabiano Rosas
2023-01-04 21:58 ` Fabiano Rosas [this message]
2023-01-04 21:58 ` [RFC PATCH 03/27] target/arm: Fix checkpatch brace errors " Fabiano Rosas
2023-01-04 21:58 ` [RFC PATCH 04/27] target/arm: Remove unused includes from m_helper.c Fabiano Rosas
2023-01-04 21:58 ` [RFC PATCH 05/27] target/arm: Remove unused includes from helper.c Fabiano Rosas
2023-01-04 21:58 ` [RFC PATCH 06/27] target/arm: cleanup cpu includes Fabiano Rosas
2023-01-04 21:58 ` [RFC PATCH 07/27] target/arm: rename handle_semihosting to tcg_handle_semihosting Fabiano Rosas
2023-01-04 22:22 ` Philippe Mathieu-Daudé
2023-01-04 21:58 ` [RFC PATCH 08/27] target/arm: wrap psci call with tcg_enabled Fabiano Rosas
2023-01-04 21:58 ` [RFC PATCH 09/27] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() Fabiano Rosas
2023-01-04 21:58 ` [RFC PATCH 10/27] target/arm: Move PC alignment check Fabiano Rosas
2023-01-04 21:58 ` [RFC PATCH 11/27] target/arm: only perform TCG cpu and machine inits if TCG enabled Fabiano Rosas
2023-01-04 21:58 ` [RFC PATCH 12/27] target/arm: Add tcg/meson.build Fabiano Rosas
2023-01-04 22:23 ` Philippe Mathieu-Daudé
2023-01-04 21:58 ` [RFC PATCH 13/27] target/arm: move translate modules to tcg/ Fabiano Rosas
2023-01-04 22:24 ` Philippe Mathieu-Daudé
2023-01-04 21:58 ` [RFC PATCH 14/27] target/arm: Move regime_using_lpae_format into internal.h Fabiano Rosas
2023-01-05 4:48 ` Richard Henderson
2023-01-04 21:58 ` [RFC PATCH 15/27] target/arm: move helpers to tcg/ Fabiano Rosas
2023-01-05 4:49 ` Richard Henderson
2023-01-04 21:58 ` [RFC PATCH 16/27] target/arm: only build psci for TCG Fabiano Rosas
2023-01-04 21:58 ` [RFC PATCH 17/27] target/arm: Extract cpustate list manipulation to a file Fabiano Rosas
2023-01-05 4:55 ` Richard Henderson
2023-01-04 21:58 ` [RFC PATCH 18/27] target/arm: Move cpregs code out of cpu.h Fabiano Rosas
2023-01-05 4:55 ` Richard Henderson
2023-01-04 21:58 ` [RFC PATCH 19/27] target/arm: Move common cpregs code into a separate file Fabiano Rosas
2023-01-05 4:58 ` Richard Henderson
2023-01-05 13:12 ` Fabiano Rosas
2023-01-04 21:58 ` [RFC PATCH 20/27] target/arm: Move cpregs definitions into tcg/cpregs.c Fabiano Rosas
2023-01-05 5:02 ` Richard Henderson
2023-01-04 21:58 ` [RFC PATCH 21/27] target/arm: make further preparation for the exception code to move Fabiano Rosas
2023-01-05 5:02 ` Richard Henderson
2023-01-04 21:58 ` [RFC PATCH 22/27] target/arm: Move hflags code into the tcg directory Fabiano Rosas
2023-01-05 5:09 ` Richard Henderson
2023-01-04 21:58 ` [RFC PATCH 23/27] tests: do not run test-hmp on all machines for ARM KVM-only Fabiano Rosas
2023-01-04 21:58 ` [RFC PATCH 24/27] tests: do not run qom-test " Fabiano Rosas
2023-01-04 21:58 ` [RFC PATCH 25/27] tests: device-introspect-test: cope with ARM TCG-only devices Fabiano Rosas
2023-01-04 21:58 ` [RFC PATCH 26/27] cpu-defs.h: Expose CPUTLBEntryFull to non-TCG code Fabiano Rosas
2023-01-05 5:12 ` Richard Henderson
2023-01-05 5:16 ` Richard Henderson
2023-01-04 21:58 ` [RFC PATCH 27/27] target/arm: don't access TCG code when debugging with KVM Fabiano Rosas
2023-01-05 5:19 ` Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230104215835.24692-3-farosas@suse.de \
--to=farosas@suse.de \
--cc=agraf@csgraf.de \
--cc=alex.bennee@linaro.org \
--cc=cfontana@suse.de \
--cc=cohuck@redhat.com \
--cc=ehabkost@redhat.com \
--cc=pbonzini@redhat.com \
--cc=peter.maydell@linaro.org \
--cc=philmd@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).