From: Jonathan Cameron via <qemu-devel@nongnu.org>
To: Gregory Price <gourry.memverge@gmail.com>
Cc: <qemu-devel@nongnu.org>, <linux-cxl@vger.kernel.org>,
<alison.schofield@intel.com>, <dave@stgolabs.net>,
<a.manzanares@samsung.com>, <bwidawsk@kernel.org>,
<gregory.price@memverge.com>, <hchkuo@avery-design.com.tw>,
<cbrowy@avery-design.com>, <ira.weiny@intel.com>
Subject: Re: [RFC v4 2/3] tests/qtest/cxl-test: whitespace, line ending cleanup
Date: Thu, 5 Jan 2023 14:38:07 +0000 [thread overview]
Message-ID: <20230105143807.0000315a@huawei.com> (raw)
In-Reply-To: <20221128150157.97724-3-gregory.price@memverge.com>
On Mon, 28 Nov 2022 10:01:56 -0500
Gregory Price <gourry.memverge@gmail.com> wrote:
> Defines are starting to exceed line length limits, align them for
> cleanliness before making modifications.
>
> Signed-off-by: Gregory Price <gregory.price@memverge.com>
Hi Gregory,
I was just reordering my tree and noticed that you've only
gone with 2 space indent. Given 4 spaces is the convention in QEMU
for other uses, I've switched my local copy of this over to 4 spaces.
Note there was also a single inconsistent 1 space indent - see below.
Jonathan
>
> ---
> tests/qtest/cxl-test.c | 99 +++++++++++++++++++++++-------------------
> 1 file changed, 54 insertions(+), 45 deletions(-)
>
> diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c
> index c54f18e76b..e59ba22387 100644
> --- a/tests/qtest/cxl-test.c
> +++ b/tests/qtest/cxl-test.c
> @@ -8,55 +8,64 @@
> #include "qemu/osdep.h"
> #include "libqtest-single.h"
>
> -#define QEMU_PXB_CMD "-machine q35,cxl=on " \
> - "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \
> - "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.size=4G "
> -
> -#define QEMU_2PXB_CMD "-machine q35,cxl=on " \
> - "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \
> - "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \
> - "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G "
> -
> -#define QEMU_VIRT_2PXB_CMD "-machine virt,cxl=on " \
> - "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \
> - "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \
> - "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G "
> -
> -#define QEMU_RP "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 "
> +#define QEMU_PXB_CMD \
> + "-machine q35,cxl=on " \
> + "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \
> + "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.size=4G "
> +
> +#define QEMU_2PXB_CMD \
> + "-machine q35,cxl=on " \
> + "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \
> + "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \
> + "- M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G "
This one only has one space.
> +
> +#define QEMU_VIRT_2PXB_CMD \
> + "-machine virt,cxl=on " \
> + "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \
> + "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \
> + "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G "
> +
> +#define QEMU_RP \
> + "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 "
>
> /* Dual ports on first pxb */
> -#define QEMU_2RP "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " \
> - "-device cxl-rp,id=rp1,bus=cxl.0,chassis=0,slot=1 "
> +#define QEMU_2RP \
> + "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " \
> + "-device cxl-rp,id=rp1,bus=cxl.0,chassis=0,slot=1 "
>
> /* Dual ports on each of the pxb instances */
> -#define QEMU_4RP "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " \
> - "-device cxl-rp,id=rp1,bus=cxl.0,chassis=0,slot=1 " \
> - "-device cxl-rp,id=rp2,bus=cxl.1,chassis=0,slot=2 " \
> - "-device cxl-rp,id=rp3,bus=cxl.1,chassis=0,slot=3 "
> -
> -#define QEMU_T3D "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \
> - "-object memory-backend-file,id=lsa0,mem-path=%s,size=256M " \
> - "-device cxl-type3,bus=rp0,memdev=cxl-mem0,lsa=lsa0,id=cxl-pmem0 "
> -
> -#define QEMU_2T3D "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \
> - "-object memory-backend-file,id=lsa0,mem-path=%s,size=256M " \
> - "-device cxl-type3,bus=rp0,memdev=cxl-mem0,lsa=lsa0,id=cxl-pmem0 " \
> - "-object memory-backend-file,id=cxl-mem1,mem-path=%s,size=256M " \
> - "-object memory-backend-file,id=lsa1,mem-path=%s,size=256M " \
> - "-device cxl-type3,bus=rp1,memdev=cxl-mem1,lsa=lsa1,id=cxl-pmem1 "
> -
> -#define QEMU_4T3D "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \
> - "-object memory-backend-file,id=lsa0,mem-path=%s,size=256M " \
> - "-device cxl-type3,bus=rp0,memdev=cxl-mem0,lsa=lsa0,id=cxl-pmem0 " \
> - "-object memory-backend-file,id=cxl-mem1,mem-path=%s,size=256M " \
> - "-object memory-backend-file,id=lsa1,mem-path=%s,size=256M " \
> - "-device cxl-type3,bus=rp1,memdev=cxl-mem1,lsa=lsa1,id=cxl-pmem1 " \
> - "-object memory-backend-file,id=cxl-mem2,mem-path=%s,size=256M " \
> - "-object memory-backend-file,id=lsa2,mem-path=%s,size=256M " \
> - "-device cxl-type3,bus=rp2,memdev=cxl-mem2,lsa=lsa2,id=cxl-pmem2 " \
> - "-object memory-backend-file,id=cxl-mem3,mem-path=%s,size=256M " \
> - "-object memory-backend-file,id=lsa3,mem-path=%s,size=256M " \
> - "-device cxl-type3,bus=rp3,memdev=cxl-mem3,lsa=lsa3,id=cxl-pmem3 "
> +#define QEMU_4RP \
> + "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " \
> + "-device cxl-rp,id=rp1,bus=cxl.0,chassis=0,slot=1 " \
> + "-device cxl-rp,id=rp2,bus=cxl.1,chassis=0,slot=2 " \
> + "-device cxl-rp,id=rp3,bus=cxl.1,chassis=0,slot=3 "
> +
> +#define QEMU_T3D \
> + "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \
> + "-object memory-backend-file,id=lsa0,mem-path=%s,size=256M " \
> + "-device cxl-type3,bus=rp0,memdev=cxl-mem0,lsa=lsa0,id=cxl-pmem0 "
> +
> +#define QEMU_2T3D \
> + "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \
> + "-object memory-backend-file,id=lsa0,mem-path=%s,size=256M " \
> + "-device cxl-type3,bus=rp0,memdev=cxl-mem0,lsa=lsa0,id=cxl-pmem0 " \
> + "-object memory-backend-file,id=cxl-mem1,mem-path=%s,size=256M " \
> + "-object memory-backend-file,id=lsa1,mem-path=%s,size=256M " \
> + "-device cxl-type3,bus=rp1,memdev=cxl-mem1,lsa=lsa1,id=cxl-pmem1 "
> +
> +#define QEMU_4T3D \
> + "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \
> + "-object memory-backend-file,id=lsa0,mem-path=%s,size=256M " \
> + "-device cxl-type3,bus=rp0,memdev=cxl-mem0,lsa=lsa0,id=cxl-pmem0 " \
> + "-object memory-backend-file,id=cxl-mem1,mem-path=%s,size=256M " \
> + "-object memory-backend-file,id=lsa1,mem-path=%s,size=256M " \
> + "-device cxl-type3,bus=rp1,memdev=cxl-mem1,lsa=lsa1,id=cxl-pmem1 " \
> + "-object memory-backend-file,id=cxl-mem2,mem-path=%s,size=256M " \
> + "-object memory-backend-file,id=lsa2,mem-path=%s,size=256M " \
> + "-device cxl-type3,bus=rp2,memdev=cxl-mem2,lsa=lsa2,id=cxl-pmem2 " \
> + "-object memory-backend-file,id=cxl-mem3,mem-path=%s,size=256M " \
> + "-object memory-backend-file,id=lsa3,mem-path=%s,size=256M " \
> + "-device cxl-type3,bus=rp3,memdev=cxl-mem3,lsa=lsa3,id=cxl-pmem3 "
>
> static void cxl_basic_hb(void)
> {
next prev parent reply other threads:[~2023-01-05 14:39 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-28 15:01 [RFC v4 0/3] CXL Type-3 Volatile Memory Support Gregory Price
2022-11-28 15:01 ` [RFC v4 1/3] hw/cxl: Add CXL_CAPACITY_MULTIPLIER definition Gregory Price
2022-11-28 15:01 ` [RFC v4 2/3] tests/qtest/cxl-test: whitespace, line ending cleanup Gregory Price
2023-01-05 14:38 ` Jonathan Cameron via [this message]
2023-01-30 13:11 ` Jonathan Cameron via
2023-01-30 14:38 ` Gregory Price
2022-11-28 15:01 ` [RFC v4 3/3] hw/cxl: Multi-Region CXL Type-3 Devices (Volatile and Persistent) Gregory Price
[not found] ` <CGME20221208225559uscas1p1e9e2c7c8f9a1654a5f41cef2c47859a8@uscas1p1.samsung.com>
2022-12-08 22:55 ` Fan Ni
2022-12-08 23:06 ` Gregory Price
2022-12-19 12:42 ` Jonathan Cameron via
2022-12-19 16:12 ` Gregory Price
2022-12-19 17:25 ` Jonathan Cameron via
2022-12-19 17:55 ` Gregory Price
2022-12-20 15:34 ` Jonathan Cameron via
2022-12-20 19:27 ` Gregory Price
2023-01-03 15:56 ` Jonathan Cameron via
2023-01-03 16:02 ` Gregory Price
2023-01-03 18:15 ` Jonathan Cameron via
2023-01-19 17:15 ` Gregory Price
2023-01-19 17:31 ` Jonathan Cameron via
2023-01-19 22:13 ` Gregory Price
2023-01-20 10:59 ` Jonathan Cameron via
2023-01-30 13:24 ` Jonathan Cameron via
2023-01-30 14:37 ` Gregory Price
2023-01-31 11:53 ` Jonathan Cameron via
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230105143807.0000315a@huawei.com \
--to=qemu-devel@nongnu.org \
--cc=Jonathan.Cameron@huawei.com \
--cc=a.manzanares@samsung.com \
--cc=alison.schofield@intel.com \
--cc=bwidawsk@kernel.org \
--cc=cbrowy@avery-design.com \
--cc=dave@stgolabs.net \
--cc=gourry.memverge@gmail.com \
--cc=gregory.price@memverge.com \
--cc=hchkuo@avery-design.com.tw \
--cc=ira.weiny@intel.com \
--cc=linux-cxl@vger.kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).